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Fule Li

Biography

       Fule Li was born in Zhejiang province, China, on November 1, 1974. He received the B.S. and M.S. degrees in electrical engineering from the University of XiDian in 1996, the Ph.D. degree in system and circuits from the University of TsingHua, Beijing, in 2003 for work on pipeline analog-to-digital converters. Now he is an associate professor in the Institute of Microelectronics of Tsinghua University, Beijing. His research interests include analog & mixed-signal building blocks such as data converter, sensor interface, RF transceiver, and etc., especially the high speed, high resolution pipelined ADC and current-steering DAC. He has co-authored more than 20 academic papers and 2 issued patents in related research areas.

Publications

Papers：

[1] Jingpeng Zhou, Peng Wang, Zhiqiang Luo, Fule Li, All-Digital Background Calibration of a Pipelined-SAR ADC Using the “Split ADC” Architecture, ISCAS 2023, pp.1-5, 2023.

[2] Junjie Jing, Yang Ding, Lingxiao Shen, Peng Wang, Fule Li, A Wide Input Common-mode Range Pipelined ADC Front-end with Common-mode Refreshing, NEWCAS 2023, pp.1-5, 2023.

[3] Yihang Cheng, Yaning Wang, Fule Li, Chun Zhang, Zhihua Wang, High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation, ISCAS 2023, pp.1-5, 2023.

[4] Yaoyu Li, Yanshu Guo, Wen Jia, Fule Li, Zhihua Wang, Hanjun Jiang, Current-Steering DAC Calibration Using Q-Learning, ISCAS 2023, pp.1-5, 2023.

[5] Yaning Wang, Yihang Cheng, Yongli Chen, Fule Li, Chun Zhang, Zhihua Wang, A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input, NEWCAS 2023, pp.1-5, 2023.

[6] Zhiqiang Luo, Hongyu Li, Junjie Jing, Yan Chen, Yutong Zhang, Fule Li, A Dual Mode SAR ADC with Oversampling and Dithering for Extended Accuracy, pp.1-4, 2022.

[7] Haoran Wang, Junjie Jing, Fule Li, A Self-Regulating Negative Charge Pump Using Multi-Phase Clock for Wideband ADCs, ISCAS 2022, pp.2525-2528, 2022.

[8] Zhiqiang Luo, Peng Wang, Fule Li, Chun Zhang, Zhihua Wang, A statistics-based background capacitor mismatch calibration algorithm for SAR ADC, ICTA 2022, pp.60-61, 2022.

[9] Yihang Cheng, Lingxiao Shen, Fule Li, Chun Zhang, Zhihua Wang, An op-amp for 12bit 1.25GS/s pipelined ADC with negative impedance compensation in 65nm CMOS, ICSICT 2022, pp.1-3, 2022.

[10] Junjie Jing, Lingxiao Shen, Fule Li, Chun Zhang, Zhihua Wang, BICMOS residue amplifier with base current compensation technique in High-speed Pipelined ADC, ICSICT 2022, pp.1-3, 2022.

[11] Meng Ni,Xiao Wang,Fule Li,Zhihua Wang, A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.29, No.7, pp.1416-1427, 2021.

[12] Meng Ni,Xiao Wang,Fule Li,Woogeun Rhee,Zhihua Wang, A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.PP, No.99, pp.1-14, 2021.

[13] Peilin Yang,Fule Li,Zhihua Wang, A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC, ISCAS 2021, pp.1-5, 2021.

[14] Shaoquan Gao,Hanjun Jiang,Fule Li,Zhihua Wang, A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers, Science China (Information Sciences), Vol.63, pp. 229404:1 - 229404:3, 2020.

[15] Peilin Yang,Xiao Wang,Chengwei Wang,Fule Li,Hanjun Jiang,Zhihua Wang, A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.28, No.9, pp. 2004 - 2013, 2020.

[16] Xiao Wang,Fule Li,Zhihua Wang, A Simple Histogram-based Capacitor Mismatch Calibration in SAR ADCs, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.PP, No.99, pp. 1 - 1, 2020.

[17] Meng Ni,Xiao Wang,Zhe Zhou,Yang Ding,Fule Li,Woogeun Rhee,Zhihua Wang, A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC, MWSCAS 2020, pp. 345 - 348, 2020.

[18] Meng Ni,Xiao Wang,Zhe Zhou,Yang Ding,Fule Li,Woogeun Rhee,Zhihua Wang, A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique, MWSCAS 2020, pp. 341 - 344, 2020.

[19] Xiao Wang,Fule Li,Wen Jia,Zhihua Wang, A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.66, No.3, pp. 322 - 326, 2019.

[20] Shaoquan Gao,Hanjun Jiang,Fule Li,Zhihua Wang, DCO gain calibration technique in fractional-N Δ-Σ PLL based two-point phase modulators, MWSCAS 2019, pp. 718 - 721, 2019.

[21] Lingxiao Shen,Fule Li,Zhihua Wang, A 10b 50 MS/s single-Channel asynchronous SAR ADC with two alternate comparators and comparator calibration, ICTA 2019, pp. 35 - 36, 2019.

[22] Zekai Wu,Fule Li,Meng Ni,Yang Ding,Zhihua Wang, A Background Timing Skew Calibration Technique in Time-Interleaved ADCs, EDSSC 2019, pp. 1 - 3, 2019.

[23] Shaoquan Gao,Hanjun Jiang,Zhaoyang Weng,Yanshu Guo,Jingjing Dong,Fule Li,Zhihua Wang, A 7.9 μA multi-step phase-domain ADC for GFSK demodulators, Analog Integrated Circuits and Signal Processing, Vol.94, pp. 49 - 63, 2018.

[24] Zhaoyang Weng,Hanjun Jiang,Jingjing Dong,Yang Li,Jingyi Zheng,Yiyu Shen,Fule Li,Woogeun Rhee,Zhihua Wang, 400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.65, No.2, pp. 745 - 757, 2018.

[25] Hongyu Li,Fule Li,Weitao Li,Hanjun Jiang,Zhihua Wang, Design of a 5GS/s 200 MHz BW 74.8 dB SNDR continuous-time sigma delta modulator in 28nm CMOS, ISNE 2018, pp. 1 - 4, 2018.

[26] Chengwei Wang,Xiao Wang,Yang Ding,Fule Li,Zhihua Wang, A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique, ISCAS 2018, pp. 1 - 5, 2018.

[27] Xiao Wang,Chengwei Wang,Fule Li,Zhihua Wang, A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process, ISCAS 2018, pp. 1 - 5, 2018.

[28] Zekai Wu,Chengwei Wang,Yang Ding,Fule Li,Zhihua Wang, An ADC Input Buffer with Optimized Linearity, ICSICT 2018, pp. 1 - 3, 2018.

[29] Xiuju He,Chunying Xue,Ya Wang,Fule Li,Chun Zhang,Xueping Jiang, An 11bit 150MS/s Sub-range SAR ADC IP for Wireless Transceiver, Microelectronics & Computer, Vol.34, No.5, pp. 1 - 5, 2017.

[30] Xiuju He,Xian Gu,Weitao Li,Hanjun Jiang,Fule Li,Zhihua Wang, An 11-bit 200MS/s Subrange SAR ADC with Low-Cost Integrated Reference Buffer, Journal of Semiconductors, Vol.38, No.10, pp. 88-93, 2017.

[31] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shuai Yuan,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang, A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS, IEEE Journal of Solid-State Circuits, Vol.52, No.11, pp. 2963 - 2978, 2017.

[32] Jingjing Dong,Hanjun Jiang,Kai Yang,Zhaoyang Weng,Fule Li,Jianjun Wei,Yanqing Ning,Xinkai Chen,Zhihua Wang, A wireless body sound sensor with a dedicated compact chipset, Circuits Systems and Signal Processing, Vol.36, No.6, pp. 2341 - 2359, 2017.

[33] Jia Liu,Fule Li,Weitao Li,Hanjun Jiang,Zhihua Wang, A Flash ADC with low offset dynamic Comparators, EDSSC 2017, pp. 1 - 2, 2017.

[34] Xuqiang Zheng,Fangxu Lv,Feng Zhao,Shigang Yue,Chun Zhang,Ziqiang Wang,Fule Li,Hanjun Jiang,Zhihua Wang, A 10 GHz 56 fsrms-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS, CICC 2017, pp. 1 - 4, 2017.

[35] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shigang Yue,Ziqiang Wang,Fule Li,Hanjun Jiang,Zhihua Wang, A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS, CICC 2017, pp. 1 - 4, 2017.

[36] Weitao Li,Fule Li,Jia Liu,Hongyu Li,Zhihua Wang, A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator, A-SSCC 2017, pp. 225 - 228, 2017.

[37] Ruihan Pei, Jia Liu,Xian Tang,Fule Li,Zhihua Wang, A low-offset dynamic comparator with input offset-cancellation, ASICON 2017, pp. 132 - 135, 2017.

[38] Honghao Chu,Fule Li, A 14bit 320MS/s pipelined-SAR ADC based on multiplexing of dynamic amplifier, ASICON 2017, pp. 628 - 631, 2017.

[39] Xuqiang Zheng,Fule Li,Zhijun Wang,Weitao Li,Wen Jia,Zhihua Wang,Shigang Yue, An S/H circuit with parasitics optimized for IF-sampling, Journal of Semiconductors, Vol.37, No.6, pp. 065005-1 - 5, 2016.

[40] Heng Liu,Hanjun Jiang,Jingpei Xia,Zhexiang Chi,Fule Li,Zhihua Wang, A Fully Integrated SoC for Smart Capsule Providing In-Body Continuous pH and Temperature Monitoring, Journal of Semiconductor Technology and Science, Vol.16, No.5, pp. 542 - 549 , 2016.

[41] Xuqiang Zheng,Zhijun Wang,Fule Li,Feng Zhao,Shigang Yue,Chun Zhang,Zhihua Wang, A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.63, No.9, pp. 1381 - 1392, 2016.

[42] Zhaoyang Weng,Hanjun Jiang,Jingjing Dong,Fule Li,Zhihua Wang, 400–450 MHz power amplifier with high-order harmonic suppression for multi-protocol transceiver , Electronics Letters, Vol.52, No.23, pp. 1927 - 1929, 2016.

[43] Zhaoyang Weng,Hanjun Jiang,Jingjing Dong,Fule Li,Zhihua Wang, 400–450 MHz power amplifier with high-order harmonic suppression for multi-protocol transceiver, Electronics Letters, Vol.52, No.23, pp. 1927-1929, 2016.

[44] Zhaoming Wu,Chun Zhang,Fule Li,Zhihua Wang, High Speed Serial Interface Transceiver Controller Based on JESD204B, NEWCAS 2016, pp. 1 - 4, 2016.

[45] Shushu Wei,XiuJu He,Fule Li,Zhihua Wang, An 11-bit 200MS/s Subrange SAR ADC with Charge-Compensation-Based Reference Buffer, NEWCAS 2016, pp. 1 - 4, 2016.

[46] Ying Ju,Fule Li,XiuJu He,Chun Zhang,Zhihua Wang, Aperture Error Reduction Technique for Subrange SAR ADC, NEWCAS 2016, pp. 1 - 4, 2016.

[47] Shushu Wei,Xian Gu,Fule Li,Zhihua Wang, An 11-bit 250MS/s subrange-SAR ADC in 40nm CMOS, ISNE 2016, pp. 1 - 2, 2016.

[48] Ying Ju,Fule Li,Xian Gu,Chun Zhang,Zhihua Wang, Digital Calibration Technique for Subrange ADC Based on SAR Architecture, ISNE 2016, pp. 1 - 2, 2016.

[49] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang, A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS , ESSCIRC 2016, pp. 305 - 308, 2016.

[50] Meng Ni,Fule Li,Jia Zhou,Zhijun Wang,Chun Zhang,Xian Tang,Zhihua Wang, A 12Bit 800MS/s time-interleaving pipeline ADC in 65nm CMOS, EDSSC 2016, pp. 391 - 394, 2016.

[51] Ya Wang,Chunying Xue,Fule Li,Chun Zhang,Zhihua Wang, A low power 11-bit 100MS/s SAR ADC IP, Journal of Semiconductors, Vol.36, No.2, pp. 025003-5, 2015.

[52] Jia Zhou,Lili Xu,Fule Li,Zhihua Wang, A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy, Journal of Semiconductors, Vol.36, No.8, 2015.

[53] Ya Wang,Chunying Xue,Fule Li,Chun Zhang,Zhihua Wang, A low power 11-bit 100 MS/s SAR ADC IP, Journal of Semiconductors, Vol.36, No.2, pp. 025003-1-5, 2015.

[54] Weitao Li,Fule Li,Changyi Yang,Minzeng Li,Zhihua Wang, A power-efficient reference buffer with wide swing for switched-capacitor ADC, Microelectronics Journal, Vol.46, No.5, pp. 410 - 414, 2015.

[55] Qi Peng,Chun Zhang,Xijin Zhao,Xuguang Sun,Fule Li,Hong Chen,Zhihua Wang, A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication, IEEE Transactions on Industrial Electronics, Vol.62, No.7, pp. 4455 - 4465, 2015.

[56] Weitao Li,Fule Li,Changyi Yang,Shengjing Li, Zhihua Wang, A 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC, China Communications, Vol.12, No.5, pp. 14 - 21, 2015.

[57] Weitao Li,Fule Li,Changyi Yang,Shengjing Li,Zhihua Wang, An 85mW 14-bit 150MS/s pipelined ADC with a merged first and second MDAC, China Communications, Vol.12, No.5, pp. 14 - 21, 2015.

[58] Shengjing Li,Weitao Li,Fule Li,Zhihua Wang,Chun Zhang, A digital blind background calibration algorithm for pipelined ADC, NEWCAS 2015, pp. 1 - 4, 2015.

[59] Weitao Li,Fule Li,Ya Wang,Shengjing Li,Chun Zhang,Zhihua Wang, A power-efficient 14-bit 250MS/s pipelined ADC, NEWCAS 2015, pp. 1 - 4, 2015.

[60] Weidong Cao,Ziqiang Wang,Dongmei Li,Xuqiang Zheng,Ke Huang,Shuai Yuan,Fule Li,Zhihua Wang, A 40Gb/s 27mW 3-tap Closed-loop Decision Feedback Equalizer in 65nm CMOS, NEWCAS 2015, pp. 1 - 4, 2015.

[61] Jifang Wu,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang, A 14-bit 200MS/s low-power pipelined flash-SAR ADC, MWSCAS 2015, pp. 1 - 4, 2015.

[62] Weidong Cao,Ziqiang Wang,Dongmei Li,Xuqiang Zheng,Fule Li,Chun Zhang,Zhihua Wang, A 40Gb/s 39mW 3-tap Adaptive Closed-loop Feedback Equalizer in 65nm CMOS, MWSCAS 2015, pp. 1 - 4, 2015.

[63] Heng Liu,Hanjun Jiang,Kai Yang,Zhexiang Chi,Fule Li,Chun Zhang,Zhihua Wang, A Fully Integrated Wireless SoC for In-Body pH and Temperature Continuous Monitoring, ISOCC 2015, 2015.

[64] Ya Wang,Fule Li,Chunying Xue,Zhihua Wang, Charge-compensation-based reference technique for switched-capacitor ADCs, ISCAS 2015, pp. 2257 - 2260, 2015.

[65] Shihao You,Fule Li,Chun Zhang,Zhihua Wang, High speed serial interface transmitter controller based on JESD204B for 1GSPS ADCs, EDSSC 2015, pp. 87 - 90, 2015.

[66] Weidong Cao,Ziqiang Wang,Dongmei Li,Fule Li,Zhihua Wang, A 40Gb/s Adaptive Equalizer with Amplitude Approaching Technique in 65nm CMOS, EDSSC 2015, pp. 451 - 454, 2015.

[67] Weidong Cao,Xuqiang Zheng,Ziqiang Wang,Dongmei Li,Fule Li,Shigang Yue,Zhihua Wang, A 15Gb/s Wireline Repeater in 65nm CMOS Technology, EDSSC 2015, pp. 590 - 593, 2015.

[68] Meng Ni,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang, A High-Speed analog front-end circuit used in a 12bit 1GSps Pipeline ADC, ASICON 2015, pp. 1 - 4, 2015.

[69] Xian Gu,Xiuju He,Fule Li, A Calibration Technique for SAR ADC Based on Code Density Test, ASICON 2015, pp. 1 - 4, 2015.

[70] Minzeng Li,Fule Li,Chun Zhang, Pixel-level A/D Conversion Using Charge Reset Technique, Semiconductor Technology, Vol.39, No.9, pp. 656 - 660+665, 2014.

[71] Yang Yang,Fule Li,Chun Zhang, Design of a 16-bit 1GSPS Current-Steering D-to-A Converter, Microelectronics, Vol.44, No.3, 2014.

[72] Ning Xu,Fule Li,Chun Zhang,Zhihua Wang, An IP-oriented 11-bit 160 MS/s 2-channel current-steering DAC, Journal of Semiconductors, Vol.35, No.12, pp. 125011-1-5, 2014.

[73] Minzeng Li,Fule Li,Chun Zhang,Zhihua Wang, Pixel-level A/D conversion using voltage reset technique, Journal of Semiconductors, Vol.35, No.11, pp. 115009-1-5, 2014.

[74] Jingjing Dong,Hanjun Jiang,Lingwei Zhang,Jianjun Wei,Fule Li,Chun Zhang,ZhiHua Wang, A low-power DC offset calibration method independent of IF gain for zero-IF receiver, Science China-Information Sciences, Vol.57, No.10, pp 1 - 10, 2014.

[75] Chunying Xue,Ya Wang,Fule Li,Chun Zhang,Zhihua Wang, An 11-bit 200MS/s SAR ADC IP for Wireless Communication SOC, ICSICT 2014, pp. 1 - 3, 2014.

[76] Jifang Wu,Fule Li,Chun Zhang, An asynchronous SAR ADC with gate-controlled ring oscillator for multi-phase clock generator, ICSICT 2014, pp. 1 - 3, 2014.

[77] Jifang Wu,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang, A 14b 200MHz power-efficient pipelined flash-SAR ADC, ICSICT 2014, pp. 1 - 3, 2014.

[78] Lili Xu,Chenchen Zhao,Fule Li,Chun Zhang,Zhihua Wang, A improved frontend for high-speed SHA-less pipelined ADC, EDSSC 2014, pp. 1 - 2, 2014.

[79] Jianjun Wei,Hanjun Jiang,Lingwei Zhang,Jinjin Dong,Fule Li,Zhihua Wang,Chun Zhang, A wide range sigma-delta fractional-N frequency synthesizer with adaptive frequency calibration, Journal of Semiconductors, Vol.34, No.6, pp. 065002-1-5, 2013.

[80] Meng Yu,Lipeng Wu,Fule Li,Zhihua Wang, An 8 bit 12 MS/s asynchronous successive approximation register ADC with an on-chip reference, Journal of Semiconductors, Vol.34, No.2, pp. 025010-1-5, 2013.

[81] Lingwei Zhang,Hanjun Jiang,Jianjun Wei,Jingjing Dong,Fule Li,Weitao Li,Jia Gao,Jianwei Cui,Baoyong Chi, Chun Zhang, Zhihua Wang, A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO, IEEE Journal of Solid-State Circuits, Vol.48, No.11, pp. 2705 - 2716, 2013.

[82] Lingwei Zhang,Hanjun Jiang,Fule Li,Jingjing Dong,Jianwei Cui,Zhihua Wang, DC offset calibration method for zero-IF receiver removing the PGA-gain-correlated offset residue, AEU-International Journal of Electronics and Communications, Vol.67, No.7, pp. 578 - 584, 2013.

[83] Zhihua Wang,Hanjun Jiang,Kai Yang,Lingwei Zhang,Jianjun Wei,Fule Li,Baoyong Chi,Chun Zhang,Shouhao Wu, Qingliang Lin, Wen Jia, Lifetime Tracing of Cardiopulmonary Sounds with Ultra-Low-Power Sound Sensor Stick Connected to Wireless Mobile Network, NEWCAS 2013, pp. 1 - 4, 2013.

[84] Chenchen Zhao,Lili Xu,Fule Li,Zhihua Wang, An efficient calibration technique for pipeline ADC, MWSCAS 2013, pp. 669 – 672, 2013.

[85] Weitao Li,Cao Sun,Fule Li,Zhihua Wang, A 14-bit Pipelined ADC with Digital Background Nonlinearity Calibration, ISCAS 2013, pp. 2448 - 2451, 2013.

[86] Lingwei Zhang,Hanjun Jiang,Fule Li,Jingjing Dong,Zhihua Wang, A LUT-free DC Offset Calibration Method for removing the PGA-gain-correlated Offset Residue, ISCAS 2013, pp. 1704 - 1707, 2013.

[87] Changyi Yang,Weitao Li,Fule Li,Zhihua Wang, A Merged First and Second Stage for Low Power Pipelined ADC, ISCAS 2013, pp. 153 – 156, 2013.

[88] Changyi Yang,Fule Li,Weitao Li,Xuan Wang,Zhihua Wang, An 85mW 14-bit 150MS/s Pipelined ADC with 71.3dB Peak SNDR in 130nm CMOS, A-SSCC 2013, pp. 85 - 88, 2013.

[89] Jianjian Shao,Weitao Li,Cao Sun,Fule Li,Chun Zhang,Zhihua Wang, A digital background calibration algorithm of a pipeline ADC based on output code calculation, Chinese Journal of Semiconductors, Vol.33, No.11, pp. 115010-1-5, 2012.

[90] Shaopeng Wang,Yannan Ren,Fule Li,Zhihua Wang, A 400MS/s 12-bit current-steering D/A Converter, Chinese Journal of Semiconductors, Vol.33, No.8, pp. 085006-1-5, 2012.

[91] Kaimin Zhou,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors, Chinese Journal of Semiconductors, Vol.33, No.6, 2012.

[92] Xuan Wang,Changyi Yang,Xiaoxiao Zhao,Chao Wu,Fule Li,Zhihua Wang,Bin Wu, A 12-bit, 270MS/s Pipelined ADC with SHA-Eliminating Front End, ISCAS 2012, pp. 798 – 801, 2012.

[93] Cao Sun,Fule Li,Weitao Li,Hanjun Jiang, A configurable active-RC filter for half-duplex transceiver, ICSICT 2012, pp. 1 - 3, 2012.

[94] Lipeng Wu,Meng Yu,Fule Li, An on-chip smart temperature sensor based on band gap and SAR ADC, ICSICT 2012, pp. 1 - 3, 2012.

[95] Wu Chao,Fule Li, A New Calibration Technique for Pipelined A/D Converters, ICETCE 2012, 2012.

[96] Ruihao Si,Fule Li,Chun Zhang, A 100MHz S/s, 7 bit VCO-based ADC which is used in Time Interleaved ADC Architectures, CECNet 2012, pp. 4 - 7, 2012.

[97] Lingwei Zhang,Hanjun Jiang,Jianjun Wei,Jingjing Dong,Weitao Li,Jia Gao,Jianwei Cui,Fule Li,Baoyong Chi, Chun Zhang, Zhihua Wang, A low-power reconfigurable multi-band sliding-IF transceiver for WBAN Hubs in 0.18μm CMOS, A-SSCC 2012, pp. 77 - 80, 2012.

[98] Xiaoyu Zhang,Hanjun Jiang,Songyuan Cheng,Lingwei Zhang,Fule Li,Chun Zhang,Zhihua Wang, A High-Efficiency Work-on-Demand SoC with a 0.9V/165 mu W MCU and Dual-Band RF for WBSN, Chinese Journal of Electronics, Vol.20, No.1, pp. 21 - 26, 2011.

[99] Kaimin Zhou,Ziqiang Wang,Fule Li,Chun Zhang,Zhihua Wang, A low-power high-linearity symmetrical readout circuit for capacitive sensors, MWSCAS 2011, pp. 1 - 4, 2011.

[100] Binjie Zhu,Hanjun Jiang,Liyuan Liu,Jigang Shao,Liwei Deng,Fule Li,Chun Zhang,Zhihua Wang, A Wireless SoC for Alimentary Canal pH Value Continuously Monitoring, MWSCAS 2011, pp. 1 - 4, 2011.

[101] Shun Zhang,Weitao Li,Fule Li, A 400-440MHz Power Amplifier for Single-chip Wireless Transceiver, ITC-CSCC 2011, 2011.

[102] Ying Cheng,Fule Li,Xuqiang Zheng,Chun Zhang, Self-Calibrating On-Chip Termination Resistor for High-Speed SerDes, CECNet 2011, pp. 5207 - 5210, 2011.

[103] Xiaoxiao Zhao,Fule Li,Bin Wu, A SHA-less 12-bit 200-MS/s pipeline ADC, ASID 2011, pp. 161 - 164, 2011.

[104] Ting Li,Fule Li,Chun Zhang,Zhihua Wang, A 14bit 10MSps Low Power Pipelined ADC With 0.99pJ/step FOM, ASID 2011, pp. 150 - 153, 2011.

[105] Yafei Ye,Liyuan Liu,Fule Li,Dongmei Li,Zhihua Wang, An 8-bit 1MHz Successive Approximation Register (SAR) A/D with 7.98 ENOB, ASID 2011, pp. 139 - 142, 2011.

[106] Binjie Zhu,Ziqi Song,Dongxu Yang,Yafei Ye,Fule Li, A 8-bit 200MSmaple/s CMOS DAC, ASID 2011, pp. 198 - 200, 2011.

[107] Linlin Chen,Ziqiang Wang,Chen Jia,Fule Li,Wenhan Hao,Guannan Xu,Chun Zhang,Zhihua Wang, Zero static power remote control system and the realization of transmitter, pp. 171 - 175, 2010.

[108] Xiaobo Cai,Fule Li, Design of High-Speed High-Resolution Pipelined ADC, Electronic Engineering & Product World, pp. 25 - 31, 2010.

[109] Yi Chen,Fule Li,Hong Chen,Chun Zhang,Zhihua Wang, A low power cyclic ADC design for a wireless monitoring system for orthopedic implants, Chinese Journal of Semiconductors, Vol.30, No.8, pp. 147 - 152, 2010.

[110] Weitao Li,Fule Li,Dandan Guo,Chun Zhang,Zhihua Wang, An Undersampling 14-bit Cyclic ADC with over 100-dB SFDR, Chinese Journal of Semiconductors, Vol.31, No.2, pp. 025008-1-6, 2010.

[111] Xiaoyu Zhang,Hanjun Jiang,Songyuan Cheng,Lingwei Zhang,Fule Li,Chun Zhang,Zhihua Wang, A High-Efficiency Work-on-Demand SoC with a 0.9V/165μW MCU and Dual-Band RF for WBSN, Chinese Journal of Electronics, pp. 1 - 4, 2010.

[112] Linlin Chen,Ziqiang Wang,Chen Jia,Fule Li,Wenhan Hao,Bin Xiao,Chun Zhang,Zhihua Wang, A RF Remote-Control Transceiver with Zero-Standby Power Based on RFID Technology, PrimeAsia 2010, pp. 243 - 246, 2010.

[113] Changyi Yang,Xiaoxiao Zhao,Fule Li,Zhihua Wang, OTACAD：An Opamp Synthesis Tool Based on Simulation and Lookup Table, ICSICT 2010 , pp. 803 - 805, 2010.

[114] Shaopeng Wang,Yannan Ren,Changyi Yang,Fule Li,Zhihua Wang, A 200MS/s 10-bit Current-steering D/A Converter with On-chip Testbench, ICSICT 2010, pp. 296 - 298, 2010.

[115] Xiaobo Cai,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang, A 12bit 100MSps Pipelined ADC without Calibration, CISP 2010, pp. 3547 - 3552, 2010.

[116] Xiaoyu Zhang,Hanjun Jiang,Fule Li,Songyuan Cheng,Chun Zhang,Zhihua Wang, An Energy-Efficient SoC for Closed-Loop Medical Monitoring and Intervention, CICC 2010, pp. 1 - 4, 2010.

[117] Hanjun Jiang,Fule Li,Xinkai Chen,Yanqing Ning,Xu Zhang,Bin Zhang,Teng Ma,Zhihua Wang, A SoC with 3.9mW 3Mbps UHF Transmitter and 240μW MCU for Capsule Endoscope with Bidirectional Communication, A-SSCC 2010, pp. 1 - 4, 2010.

[118] Rui Guo,Fule Li,Chun Zhang, Design of A 13-bit 50MS/s CMOS Pipelined ADC, Semiconductor Technology, Vol.34, No.10, pp. 1022 - 1026, 2009.

[119] Guoru Li,Guolin Li,Dongmei Li,Fule Li,Baoyong Chi,Chun Zhang, A multi-standard RF filter in UMC0.18um CMOS technology, Microelectronics, Vol.5, pp. 54 - 58, 2009.

[120] Jingchao Wang,Chun Zhang,Baoyong Chi,Ziqiang Wang,Fule Li,Zhihua Wang, A Low Cost Integrated Transceiver for Mobile UHF Passive RFID Reader Applications, Chinese Journal of Semiconductors, Vol.30, No.9, pp. 095007 - 1 - 5, 2009.

[121] Yi Chen,Fule Li,Hong Chen,Chun Zhang,Zhihua Wang, A Low Power Cyclic ADC Design for the Wireless Monitoring System of the Orthopedic Implants, Chinese Journal of Semiconductors, Vol.30, No.8, pp. 147 - 152, 2009.

[122] Dandan Guo,Fule Li,Chun Zhang,Zhihua Wang, A 13-bit, 8 MSample/s Pipeline A/D Converter, Chinese Journal of Semiconductors, Vol.30, No.2, pp. 0250061 - 5, 2009.

[123] Jingyi Guo,Dongmei Li,Liyuan Liu,Fule Li, The hardware realization of a digital background calibration technique for pipelined A/D converters, Chinese High Technology Letters, Vol.19, No.3, pp. 290 - 294, 2009.

[124] Qiuling Zhu,Chun Zhang,Xiaohui Wang,Ziqiang Wang,Fule Li,Zhihua Wang, VLSI Design of Spread Spectrum Encoding Low Power RFID Tag Baseband Processor, VLSI-DAT 2009, pp. 191 – 194, 2009.

[125] Qiuling Zhu,Chun Zhang,Zhongqi Liu,Jingchao Wang,Fule Li,Zhihua Wang, A Robust Radio Frequency Identification System Enhanced with Spread Spectrum Technique, ISCAS 2009, pp. 37 - 40, 2009.

[126] Weitao Li,Fule Li,Chun Zhang,Zhihua Wang, A Digital Background Calibration Algorithm Based on Code Occurrence Count for Pipelined ADCs, ICCCAS 2009, pp. 550 - 553, 2009.

[127] Yannan Ren,Fule Li,Chun Zhang,Zhihua Wang, A 400MS/s 10-bit current-steering D/A Converter, ICCCAS 2009, pp. 533 - 536, 2009.

[128] Weitao Li,Fule Li,Dandan Guo,Chun Zhang,Zhihua Wang, An Undersampling 14-bit Cyclic ADC, ASICON 2009, pp. 211 - 214, 2009.

[129] Chao Sun,Dongmei Li,Liyuan Liu,Fule Li, A 14-Bit 20 MS/s CMOS Pipelined A/D Converter, Microelectronics, Vol.38, No.3, pp. 320 - 325, 2008.

[130] Fule Li,Jingbo Duan,Zhihua Wang, A High Linearity,13bit Pipelined CMOS ADC, Chinese Journal of Semiconductors, Vol.29, No.3, pp. 497 - 501, 2008.

[131] Fule Li,Jingbo Duan,Zhihua Wang, A Capacitor Paring Technique for Capacitor Mismatch Reduction, Acta Electronica Sinica, Vol.36, No.2, pp. 338 - 341, 2008.

[132] Shuaiqi Wang,Fule Li,Yasuaki Inoue, A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2465 - 2474, 2008.

[133] Dandan Guo,Fule Li,Jingbo Duan,Chun Zhang,Zhihua Wang, A 13-bit CMOS pipeline analog-to-digital converter with improved sampling circuits, ICCCAS 2008, pp. 1048 - 1052, 2008.

[134] Fule Li,Zhihua Wang,Dongmei Li, An incomplete settling technique for pipelined analog-to-digital converters, ISCAS 2007, pp. 3950 - 3953, 2007.

[135] Jingbo Duan,Fule Li,Liyuan Liu,Dongmei Li,Yongmin Li,Zhihua Wang, A pipelined A/D conversion technique with low INL and DNL, ISCAS 2007, pp. 3391 - 3394, 2007.

[136] Xin Zhang,Fule Li,Zhihua Wang, A Nonlinear Background Calibration Technique for Pipelined A/D, Microelectronics, pp. 2176 - 2180, 2006.

[137] Hongmei Wang,Fule Li,Dongmei Li,Zhihua Wang, A Speed Analysis Methodology for Pipelined A/D Converters, Journal of University of Electronic Science and Technology of China, Vol.35, No.6, pp. 913 - 916, 2006.

[138] Fule Li,Hongmei Wang,Dongmei Li,Zhihua Wang, Low power 13bit 10^7 sample/s A/D converter, Journal of Tsinghua University (Science and Technology), Vol.46, No.1, pp. 115 - 118, 2006.

[139] Hongmei Wang,Fule Li,Guolin Li,Zhihua Wang, Resolution analysis of the first stage in the high precision pipelined ADCs, Chinese Journal of Electronics, Vol.15, No.1, pp. 47 - 50, 2006.

[140] Fule Li,Dongmei Li,Chun Zhang,Zhihua Wang, Capacitor Error Averaging Technique for Pipelined ADCs, Journal of Tsinghua University (Science and Technology), Vol.43, No.1, pp. 63 - 66, 2003.

[141] Fule Li,Dongmei Li,Zhihua Wang, Novel method for improving the speed of pipelined A/D converters, Journal of Tsinghua University (Science and Technology), Vol.42, No.1, pp. 7 - 10, 2002.

[142] Fule Li,Dongmei Li,Chun Zhang,Zhihua Wang, An Improved Capacitor Averaging Technique for Pipelined ADCs, Acta Electronica Sinica, Vol.30, No.9, pp. 1285 - 1287, 2002.

[143] Fule Li,Dongmei Li,Chun Zhang,Zhihua Wang, A Capacitor Mismatch Calibration Technique for Pipelined A/D Conversion, Acta Electronica Sinica, Vol.30, No.11, pp. 1 - 3, 2002.

Patents：

[1] Fule Li, Zhe Zhou. A single channel data transmission circuit of multi-channel asynchronous signal based on oversampling: China, 202111563325.7[P].

[2] Fule Li, Zhe Zhou. A TSV through-hole data transmission circuit with low power consumption and low power jitter based on frequency division: China, 202111333647.2[P].

[3] Peilin Yang, Fule Li, Zhihua Wang. Capacitance split structure switched capacitor amplification circuit based on double-input transconductance operational amplifier: China, 202110505925.1[P]. 2022-11-11.

[4] Fule Li, Meng Ni, Yang Ding. Method for calibrating time sequence deviation between TI-ADC channels: China, 202010707597.9[P]. 2022-11-11.

[5] Fule Li, Yang Ding, Xiao Wang. Broadband low-power-consumption comparator circuit: China, 202010403259.6[P]. 2022-4-15.

[6] Fule Li, Zhe Zhou. Curvature compensation low-temperature drift band-gap reference voltage source circuit: China, 202010130680.4[P]. 2021-05-14.

[7] Fule Li, Yang Ding. Threshold voltage generation circuit with jitter function, FlashADC and pipelined ADC: China, 202010130663.0[P]. 2021-08-24.

[8] Fule Li，Jia Liu. A high speed CMOS transmission gate switch circuit: China, 201711453695.9[P]. 2021-05-07.

[9] Fule Li, Chengwei Wang, Wen Jia, Zhihua Wang. A method for improving the output accuracy of a pipelined ADC and an analog to digital converter: China, 201710743591.5[P]. 2020-12-08.

[10] Zhihua Wang, Hanjun Jiang, Wendi Yang, Chun Zhang, Fule Li. Implanted dynamic ECG monitor with dynamically adjusting electrode configuration: 中国, 201710518009.5[P]. 2020-02-21.

[11] Fule Li, Jia Liu, Wen Jia, Zhihua Wang. Reference voltage drive circuit: China, 201710326104.5[P]. 2020-03-24.

[12] Fule Li, Xiao Wang, Wen Jia, Zhihua Wang. Pipelined analog-to-digital converter as well as operational amplifier adaptive configuration circuit and method thereof: China, 201710326116.8[P]. 2022-04-01.

[13] Jingjing Dong, Hanjun Jiang, Shaoquan Gao, Zhaoyang Weng, Fule Li, Zhihua Wang. A phase domain analog to digital converter: China, 201710154193.X[P]. 2020-05-19.

[14] Hanjun Jiang, Zhihua Wang, Zeliang Wu, Chun Zhang, Fule Li. An implantable wireless intracranial pressure monitoring system based on airbag: China, 201710128667.3[P]. 2019-07-12.

[15] Ziqiang Wang, Naiwen Zhou, Fangxu Lv, Chun Zhang, Zhihua Wang, Fule Li. A transmitter with timing alignment: China, 201611104171.4[P]. 2020-10-27.

[16] Yajun He, Ziqiang Wang, Woogeun Rhee, Han Liu, Chun Zhang, Zhihua Wang, Fule Li. A multi-protocol phase-locked loop: China, 201611104156.X[P]. 2018-10-19.

[17] Fangxu Lv, Ziqiang Wang, Chun Zhang, Zhihua Wang, Fule Li. A high speed combiner: China, 201611104765.5[P]. 2019-07-12.

[18] Ziqiang Wang, Yuxing Zhou, Chun Zhang, Zhihua Wang, Fule Li. A Low Dropout Linear Regulator with Analog Circuit Compensation Capacitance: China, 201611104762.1[P]. 2017-12-19.

[19] Ziqiang Wang, Yuxing Zhou, Chun Zhang, Zhihua Wang, Fule Li. A Low Dropout Linear Regulator with Digital Circuit Compensation Capacitance: China, 201611105561.3[P]. 2017-12-19.

[20] Fangxu Lv, Ziqiang Wang, Chun Zhang, Zhihua Wang, Fule Li. A High Speed Low Power PAM4 Transmitter: China, 201611104172.9[P]. 2018-11-20.

[21] Fule Li, Ying Ju. Input sampling and conversion front-end circuit: China, 201610140328.2[P]. 2020-06-02.

[22] Weidong Cao, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Fule Li. A high-speed circuit dynamic latch with pull-up PMOS transistor: China, 201510497993.2[P]. 2017-12-29.

[23] Xian Tang, Fule Li, Chun Zhang, Zhihua Wang. Calibration circuit and calibration methods of resistance temperature sensor chip: China, 201510213973.8[P]. 2017-11-28.

[24] Fule Li, Chun Zhang, Zhihua Wang. Analog voltage buffer circuit with high frequency compensation: China, 201410359994.6[P]. 2017-09-22.

[25] Fule Li, Jifang Wu. A multi-phase clock generator for asynchronous SAR ADC: China, 201310714734.1[P]. 2017-01-11.

[26] Xuqiang Zheng, Ke Huang, Fule Li, Ziqiang Wang, Chun Zhang, Zhihua Wang. A clock path front-end amplifier circuit of source synchronous high-speed serial interface: China, 201310629540.1[P]. 2016-08-17.

[27] Fule Li, Lili Xu, Chun Zhang, Zhihua Wang. Front-end circuit of analog-digital converter: China, 201310217847.0[P]. 2016-06-01.

[28] Fule Li, Chun Zhang, Zhihua Wang. Front-end circuit for analogue-to-digital converter with pipeline structure and time sequence control method thereof: China, 201310146910.6[P]. 2017-03-15.

[29] Shijie Hu, Ziqiang Wang, Ke Huang, Xuqiang Zheng, Fule Li, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang. Clock phase judgment circuit and judgment method in high-speed clock data recovery circuit: China, 201210478209.X[P]. 2015-10-14.

[30] Jingjing Dong, Lingwei Zhang, Hanjun Jiang, Baoyong Chi, Fule Li, Chun Zhang, Zhihua Wang. Reconfigurable multi-frequency-range transceiver radio-frequency front end: China, 201210394086.1[P]. 2014-07-23.

[31] Fule Li, Weitao Li, Changyi Yang, Zhihua Wang. A driving circuit of reference voltage: China, 201210362016.8[P]. 2016-07-20.

[32] Fule Li, Yanqing Ning, Hanjun Jiang, Xinkai Chen, Hongmei Wang. A wireless RF transmitter: China, 201110140426.3[P]. 2016-04-20.

Papers before joining ICAS：