题目/Title：A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation

作者/Author：
                        Meng Ni,Xiao Wang,Fule Li,Zhihua Wang

期刊/Journal：IEEE Transactions on Very Large Scale Integration (VLSI) Systems

年份/Issue Date：2021May

卷（期）及页码/Volume（No.）&pages：Vol.29, No.7, pp.1416-1427

摘要/Abstract：
This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) analog-to-digital converter (ADC) utilizing an open-loop integrator-based residue amplifier (RA). The gain variation of RA under different process, voltage, and temperature (PVT) conditions is alleviated by adaptively adjusting the length of the generated integration time. A 13-bit 312.5-MS/s two-stage pipelined SAR ADC employing the presented technique is fabricated in a 28-nm process. At a sampling rate of 312.5 MS/s, the prototype ADC achieves a 65.1-dB SNDR and a Walden FoM of 13.95 fJ/conversion-step with an over Nyquist input. Less than 1-dB SNDR variation are obtained for supply voltage varying within ±60 mV and the temperature varying from -40 °C to 120 °C, respectively.