题目/Title：A 100MHz S/s, 7 bit VCO-based ADC which is used in Time Interleaved ADC Architectures

作者/Author：司瑞灏,李福乐,张春
                        Ruihao Si,Fule Li,Chun Zhang

会议/Conference：CECNet 2012

地点/Location：YiChang, Hubei, China

年份/Issue Date：2012.21-23 April

页码/pages：pp. 4 - 7

摘要/Abstract：
In this paper, principles of time interleaved ADC and VCO-based ADC architectures are introduced. A design of VCO-based ADC which is suitable to be used in time interleaved ADC architectures is presented. In the design, a high speed sample and hold circuit is realized for wideband input, multi phase ring oscillator is adopted in order to increase time resolution, multi phase edge counter is used to complete the quantization process. The proposed ADC is designed in UMC 0.18um technology. Simulation results show the proposed architecture can reach 7 bit output resolution at 100MHz speed of sample per second when a 1.037GHz input signal is applied. The proposed VCO-based ADC architecture is technology friendly for low power consumption compared to OPAMP-based ADC architectures at similar speed. This merit enables VCO-based ADC compatible to be used in time interleaved ADC architectures as technology proceeds.