Title：A multi-phase clock generator for asynchronous SAR ADC

Country：China

Patent No.：201310714734.1

Legal Status：Authorized

Inventor：Fule Li, Jifang Wu

Assignee：Tsinghua University

Address：Mailbox No. 82, Beijing 100084

Filing Date：2013-12-20

Issue Date：2017-01-11

The invention provides a multiphase clock generating circuit for an asynchronous successive approximation analog/digital converter. The multiphase clock generating circuit comprises a comparator, a NAND gate and a NOT gate, wherein the first output end and the second output end of the comparator are respectively connected with the first input end and the second input end of the NOT gate; the comparator is used for comparing input voltage signals and inputting the comparative result in the NAND gate; the NAND gate receives gating signals through the third input end of the NAND gate, and generates output signals according to the gating signals and output result of the comparator; the input end of the NOT gate is connected with the output end of the NAND gate, and the NOT gate is used for generating multiphase clock signals according to output signals. According to the embodiment of the invention, based on the principle of a gating annular oscillator, high-speed cascade interaction operation with asynchronous successive approximation logic is eliminated, so that a loop circuit for asynchronous conversion is simpler, thus the asynchronous conversion time of the asynchronous successive approximation analog/digital converter is reduced, and the conversion rate is improved. The invention also provides a control logic circuit for the synchronous successive approximation analog/digital converter.

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