Title：A multi-protocol phase-locked loop

Country：China

Patent No.：201611104156.X

Legal Status：Authorized

Inventor：Yajun He, Ziqiang Wang, Woogeun Rhee, Han Liu, Chun Zhang, Zhihua Wang, Fule Li

Assignee：Tsinghua University

Address：Tsinghua University,Haidian District Beijing 100086, China

Filing Date：2016-12-05

Issue Date：2018-10-19

The invention relates to a phase-locked loop supporting multiple protocols, which belongs to the design field of integrated circuits. The phase-locked loop supporting multiple protocols comprises a phase frequency detector, a charge pump, a low pass filter, voltage controlled oscillators and a frequency divider, wherein the two voltage controlled oscillators are arranged in parallel and at different resonance frequencies, different frequency ranges can be covered respectively, and only one voltage controlled oscillator works at the same moment; the frequency divider is a multi-mode frequency divider and comprises multiple frequency division modules with different frequency division ratios, and the output frequency signals of the currently-working voltage controlled oscillator are subjected to frequency division, the obtained signals and reference signals are compared through the phase frequency detector, control signals for the voltage controlled oscillator are then outputted through the charge pump and the low pass filter, and the frequency and the phase of the currently-working voltage controlled oscillator are locked. The phase-locked loop has the advantages of compact structure, large frequency coverage range, and multiple supported working frequency points, multiple clock frequencies can be outputted, and requirements on the transmission data rate by multiple protocols such as Ethernet, a fiber channel and RapidIO in a high-speed serial interface can be met.

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