Title：A method for improving the output accuracy of a pipelined ADC and an analog to digital converter
Country：China
Patent No.：201710743591.5
Legal Status：Authorized
Inventor：Fule Li, Chengwei Wang, Wen Jia, Zhihua Wang
Assignee：Research Institute of Tsinghua University in Shenzhen
Address：Room A302, Research Institute of Tsinghua University in Shenzhen, the Southern District of the High-tech Industrial Park, Nanshan District, Shenzhen 518057, Guangdong
Filing Date：2017-08-25
Issue Date：2020-12-08
Abstract：
The invention provides a method for improving output precision of an assembly analog-digital converter and the assembly line analog-digital converter. The assembly analog-digital converter comprises multiple serially connected polar circuits, a residual error amplifying circuit and a sub analog-digital converter are arranged at each polar circuit; the method comprises the following steps: S1, adding a calibration module in a first stage polar circuit, wherein the calibration module comprises a switch capacitor array, and the switch capacitor array comprises at least one jittering capacitor; S2, measuring and storing each sampling capacitor in the residual error amplifying capacitor and an initial weight value of each jittering capacitor when the input signal of the polar circuit is zero; and S3, calibrating a digital signal output by the polar circuit by using the initial weight value of each sampling capacitor, and finishing the jittering-elimination processing at a digital domain byusing the initial weight value of each jittering capacitor so as to finish the foreground calibration process.
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