Papers：
[1]
Jiawei Wang, Hao Xu, Ziqiang Wang, Haikun Jia, Hanjun Jiang, Chun Zhang, Zhihua Wang,
A 128 Gbps PAM-4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS,
IET CIRCUITS DEVICES & SYSTEMS,
Vol.17, No.3, pp.174-179,
2023.
[2]
Aili Ma, Peijun Li, Chun Zhang, Zhihua Wang, Ziqiang Wang,
MN-SLAM: Multi-networks Visual SLAM for Dynamic and Complicated Environments,
ICICA 2022,
pp.73-77,
2022.
[3]
Gandong Han, Weiyi Zhang, Liting Niu, Chun Zhang, Zhihua Wang, Ziqiang Wang,
Hardware Implementation of Approximate Fixed-point Divider for Machine Learning Optimization Algorithm,
PrimeAsia 2022,
pp.22-25,
2022.
[4]
Zeliang Zhao, Xin Wu, Dengjie Wang, Ziqiang Wang, Chun Zhang, Xiangyu Li, Zhihua Wang,
A 40 Gbps PAM-4 Receiver with 12-Tap Direct Decision Feedback Equalizer Employing 1.5-stage Slicers in 65-nm CMOS,
ICTA 2022,
pp.230-231,
2022.
[5]
Ziqiang Wang, Dengjie Wang, Xin Wu, Jiawei Wang, Hao Xu, Chun Zhang, Hong Chen, Zhihua Wang,
A 44 Gbps PAM-4 Transmitter with Resistance Feedback 4:1 MUX in 65nm CMOS,
ICSICT 2022,
pp.1-3,
2022.
[6]
Xin Wu, Ziqiang Wang, Zeliang Zhao, Chun Zhang, Zhihua Wang,
A 20Gbuad NRZ/PAM4 Receiver Frontend in 65nm CMOS,
ICSICT 2022,
pp.1-3,
2022.
[7]
Dengjie Wang,Ziqiang Wang,Hao Xu,Jiawei Wang,Zeliang Zhao,Chun Zhang,Zhihua Wang,Hong Chen,
A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS,
IEEE Transactions on Circuits and Systems I: Regular Papers,
Vol.PP, No.99, pp.1-14,
2021.
[8]
Hong Chen,Dengjie Wang,Ziqiang Wang,Shuai Yuan,Chun Zhang,Zhihua Wang,
An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS,
IEEE Access,
Vol.9, pp.70856-70867,
2021.
[9]
Fasih Ud Din Farrukh,Chun Zhang,Yancao Jiang,Zhonghan Zhang,Ziqiang Wang,Zhihua Wang,Hanjun Jiang,
Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders,
IEEE Open Journal of Circuits and Systems,
Vol.1, pp. 76 - 87,
2020.
[10]
Chaoxiang Yang,Xianwei Kong,Wenhuan Luan,Yuanhang Zhang,Zhijun Wang,Chun Zhang,Ziqiang Wang,
Design of the Physical Coding Sublayer Based on the Ethernet 10Gbase-R Protocol,
Microelectronics & Computer,
Vol.36, No.2, pp. 16-20,
2019.
[11]
Mao Li,Chen Jia,Wenhuan Luan,Xin Lin,Ziqiang Wang,Chun Zhang,Zhihua Wang,
A high speed transmitter with 40 bits data and variable data-width and supported multi-protocols (Original in Chinese),
Microelectronics & Computer,
Vol.36, No.9, pp. 16 - 20,
2019.
[12]
Fangxu Lv,Jianye Wang,Xuqiang Zheng,Ziqiang Wang,Yajun He,Hao Ding,Yongcong Liu,Chun Zhang,Zhihua Wang,
A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65nm CMOS Technology,
Journal of Harbin Institute of Technology (New Series),
Vol.26, No.3, pp. 50-57,
2019.
[13]
Fangxu Lv,Xuqiang Zheng,Jianye Wang,Guoli Zhang,Ziqiang Wang,Shuai Yuan,Yajun He,Chun Zhang,Zhihua Wang,
A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology,
Analog Integrated Circuits and Signal Processing,
Vol.99, No.1, pp. 147 - 157,
2019.
[14]
Dengjie Wang,Hong Chen,Wenhuan Luan,Xin Lin,Fangxu Lv,Ziqiang Wang,Hanjun Jiang,Chun Zhang,Zhihua Wang,
A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology,
MWSCAS 2019,
pp. 251 - 254,
2019.
[15]
Wenhuan Luan,Xiangyu Li,Dengjie Wang,Ziqiang Wang,Xin Lin,Mao Li,
A 1.25-8.5 Gb/s wide range CDR with locking detector in 40 nm CMOS technology,
EDSSC 2019,
pp. 1 - 3,
2019.
[16]
Chaoxiang Yang,Chung Zhang,Ziqiang Wang,Zhijun Wang,Xiang Xie,Hanjun Jiang,
Design of Elastic Buffer in Physical Coding Sublayer Based on 10Gbase-KR,
Microelectronics & Computer,
Vol.35, No.3, pp. 14 - 18,
2018.
[17]
Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shuai Yuan,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang,
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS,
IEEE Journal of Solid-State Circuits,
Vol.52, No.11, pp. 2963 - 2978,
2017.
[18]
Shuai Yuan,Liji Wu,Ziqiang Wang,Chun Zhang,Zhihua Wang,Hanjun Jiang,
A 25Gb/s Serial-Link Repeater With Receiver Equalization and Transmitter De-emphasis in 0.13μm SiGe BiCMOS,
MWSCAS 2017,
pp. 527 - 530,
2017.
[19]
Yajun He,Ziqiang Wang,Han Liu,Fangxu Lv,Shuai Yuan,Chun Zhang,Zhihua Wang,Hanjun Jiang,
An 8.5–12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes,
MWSCAS 2017,
pp. 791 - 794,
2017.
[20]
Fangxu Lv,Xuqiang Zheng,Shuai Yuan,Ziqiang Wang,Yajun He,Chun Zhang,Zhihua Wang,Fangxu Lv,Jianye Wang,
A 40-80Gb/s PAM4 Wireline Transmitter in 65nm CMOS Technology,
MWSCAS 2017,
pp. 539 - 542,
2017.
[21]
Mao Li,Yuxing Zhou,Dengjie Wang,Shuai Yuan,Wenhuan Luan,Xin Lin,Ziqiang Wang,Chun Zhang,Xiang Xie,
A max mode control LDO with a good behavior at PSRR and line regulation and load regulation,
EDSSC 2017,
pp. 1 - 2,
2017.
[22]
Xin Lin,Ziqiang Wang,Yajun He,Yuxing Zhou,Chun Zhang,Wenhuan Luan,Mao Li,
An 8-11GHz low phase noise ring voltage controlled oscillator,
EDSSC 2017,
pp. 1 - 2,
2017.
[23]
Wenhuan Luan,Ziqiang Wang,Shuai Yuan,Chun Zhang,Zhihua Wang,
A 13.3W 5-Gb/s two-dimensional eye-opening monitor in 40nm CMOS technology,
EDSSC 2017,
pp. 1 - 2,
2017.
[24]
Shuai Yuan,Ziqiang Wang,Yajun He,Fangxu Lv,Chun Zhang,Zhihua Wang,Hanjun Jiang,
A 1.25–12.5Gb/s 5.28mW/Gb/s multi-standard serial-link transceiver with 32dB of equalization in 40nm CMOS,
EDSSC 2017,
pp. 1 - 2,
2017.
[25]
Chaoxiang Yang,Chung Zhang,Wenao Xie,Ziqiang Wang,Zhijun Wang,Xiang Xie,
Design of the Critical Controller in Physical Coding Sublayer Based on the 10Gbase-KR Protocol,
EDSSC 2017,
2017.
[26]
Yajun He,Ziqiang Wang,Han Liu,Fangxu Lv,Shuai Yuan,Chun Zhang,Xiang Xie,Hanjun Jiang,
An 8.5-12.5GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes,
EDSSC 2017,
pp. 1 - 2,
2017.
[27]
Fangxu Lv,Jianye Wang,Heming Wang,Ziqiang Wang,Yajun He,Yongcong Liu,Chun Zhang,Zhihua Wang,Hanjun Jiang,
A 10 GHz Ring-VCO Based Injection-Locked Clock Multiplier for 40 Gb/s SerDes Application in 65 nm CMOS Technology,
EDSSC 2017,
pp. 1 - 2,
2017.
[28]
Fangxu Lv,Xuqiang Zheng,Ziqiang Wang,Yajun He,Chun Zhang,Jianye Wang,Zhihua Wang,Hanjun Jiang,
Design of 80-Gb/s PAM4 Wireline Receiver in 65-nm CMOS Technology,
EDSSC 2017,
pp. 1 - 2,
2017.
[29]
Fangxu Lv,Jianye Wang,Xuqiang Zheng,Shuai Yuan,Ziqiang Wang,Yajun He,Zhihua Wang,Hanjun Jiang,
A 10–60 Gb/s wireline transmitter with a 4-tap multiple-MUX based FFE,
EDSSC 2017,
pp. 1 - 2,
2017.
[30]
Xuqiang Zheng,Fangxu Lv,Feng Zhao,Shigang Yue,Chun Zhang,Ziqiang Wang,Fule Li,Hanjun Jiang,Zhihua Wang,
A 10 GHz 56 fsrms-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS,
CICC 2017,
pp. 1 - 4,
2017.
[31]
Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shigang Yue,Ziqiang Wang,Fule Li,Hanjun Jiang,Zhihua Wang,
A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS,
CICC 2017,
pp. 1 - 4,
2017.
[32]
Fangxu Lv,Jianye Wang,Dengjie Wang,Yongcong Liu,Ziqiang Wang,
Design of 56 Gb/s PAM4 Wire-line Receiver With Ring VCO Based CDR in a 65 nm CMOS Technology,
ASICON 2017,
pp. 537 - 540,
2017.
[33]
Jinxing Guo,Liji Wu,Yun Niu,Ziqiang Wang,Wen Jia,
An IPSec Accelerator for Online Network Security Processor SoC,
Microelectronics,
Vol.46, No.1, pp. 90 - 94,
2016.
[34]
Naihao Xu,Hanjun Jiang,Wan Wang,Ziqiang Wang,Zhihua Wang,
Current-feedback Instrumentation Amplifier with Digital Offset Calibration and Rail-to-rail Output for ECG/EEG Acquisition,
Microelectronics,
Vol.46, No.1, pp. 25 - 28,
2016.
[35]
Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang,
A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology,
IEEE Transactions on Circuits and Systems I: Regular Papers,
Vol.63, No.7, pp. 939 - 949,
2016.
[36]
Naiwen Zhou,Linghan Wu,Ziqiang Wang,Zhihua Wang,
A 28-Gb/s Transmitter with 3-tap FFE and T-coil Enhanced Terminal in 65-nm CMOS Technology,
NEWCAS 2016,
pp. 1 - 4,
2016.
[37]
Naiwen Zhou,Ke Huang,Fangxu Lv,Ziqiang Wang,Chun Zhang,Zhihua Wang,
A 76 mW 40-Gb/s SerDes Transmitter With 64:1 MUX In 65-nm CMOS Technology,
ICEIEC 2016,
pp. 155 - 158,
2016.
[38]
Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang,
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS ,
ESSCIRC 2016,
pp. 305 - 308,
2016.
[39]
Naiwen Zhou,Ertai Duo,Ziqiang Wang,Hanjun Jiang,Ke Huang,
A 3-Tap Feed-Forward-Equalizer in 65nm CMOS ,
Microelectronics,
pp. 764 - 768 ,
2015.
[40]
Weidong Cao,Chenlong Hou,Jinxing Guo,Yilin Song,Ziqiang Wang,Hanjun Jiang,Zhihua Wang,
The Design and Implementation of 20GHz VCO,
Microelectronics,
Vol.45, No.5, pp. 577 - 580,
2015.
[41]
Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang,
A 80mW 40Gb/s Transmitter with Automatic Serializing Time Window Search and 2-tap Pre-emphasis in 65nm CMOS Technology,
IEEE Transactions on Circuits and Systems I: Regular Papers,
Vol.62, No.5, pp. 1441 - 1450,
2015.
[42]
Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Wen Jia,Liji Wu,Chun Zhang,Zhihua Wang,
10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed-signal adaption in 65 nm CMOS technology,
Electronics Letters,
Vol.51, No.21, pp. 1645 - 1647,
2015.
[43]
Weidong Cao,Ziqiang Wang,Dongmei Li,Xuqiang Zheng,Ke Huang,Shuai Yuan,Fule Li,Zhihua Wang,
A 40Gb/s 27mW 3-tap Closed-loop Decision Feedback Equalizer in 65nm CMOS,
NEWCAS 2015,
pp. 1 - 4,
2015.
[44]
Weidong Cao,Ziqiang Wang,Dongmei Li,Xuqiang Zheng,Fule Li,Chun Zhang,Zhihua Wang,
A 40Gb/s 39mW 3-tap Adaptive Closed-loop Feedback Equalizer in 65nm CMOS,
MWSCAS 2015,
pp. 1 - 4,
2015.
[45]
Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Peng Wang,Wen Jia,Chun Zhang,Zhihua Wang,
A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS,
ESSCIRC 2015,
pp. 144 - 147,
2015.
[46]
Weidong Cao,Ziqiang Wang,Dongmei Li,Fule Li,Zhihua Wang,
A 40Gb/s Adaptive Equalizer with Amplitude Approaching Technique in 65nm CMOS,
EDSSC 2015,
pp. 451 - 454,
2015.
[47]
Weidong Cao,Xuqiang Zheng,Ziqiang Wang,Dongmei Li,Fule Li,Shigang Yue,Zhihua Wang,
A 15Gb/s Wireline Repeater in 65nm CMOS Technology,
EDSSC 2015,
pp. 590 - 593,
2015.
[48]
Ke Huang,Deng Luo,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang,
A 190mW 40Gbps SerDes Transmitter and Receiver Chipset in 65nm CMOS Technology,
CICC 2015,
pp. 1 - 4,
2015.
[49]
Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Wen Jia,Chun Zhang,Zhihua Wang,
A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS[C],
CICC 2015,
pp. 1 - 4,
2015.
[50]
Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Ni Xu,Woogeun Rhee,Liji Wu,Chun Zhang,
A 4.8-mW/Gb/s 9.6-Gb/s 5+1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS,
IEEE Transactions on Circuits and Systems II: Express Briefs,
Vol.61, No.4, pp. 209 - 213,
2014.
[51]
Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang,
2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology,
Electronics Letters,
Vol.50, No.25, pp. 1910 - 1912,
2014.
[52]
Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang,
2 GHz sub-harmonically injectin-locked PLL with mixer-based injection timing control in 0.18 μm CMOS technology,
Electronics Letters,
Vol.50, No.12, pp. 855 - 857,
2014.
[53]
Ziqiang Wang,Hui Jiang,Chun Zhang,Hanjun Jiang,Zhihua Wang,
A chopper current feedback instrument amplifier with bandpass amplification stage,
Analog Integrated Circuits and Signal Processing,
Vol.81, No.3, pp. 763 - 775,
2014.
[54]
Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang,
A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-mu m CMOS technology,
Analog Integrated Circuits and Signal Processing,
Vol.81, No.3, pp. 777 - 788,
2014.
[55]
Ke Huang,Ziqiang Wang,Xuqiang Zheng,Kunzhi Yu,Chun Zhang,Zhihua Wang,
A 5+ 1-lane 3-10 Gbps 3.5 mW/Gb/s source synchronous receiver in 65 nm CMOS technology,
Analog Integrated Circuits and Signal Processing,
Vol.80, No.3, pp. 519 - 529,
2014.
[56]
Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang,
A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology,
Analog Integrated Circuits & Signal Processing,
Vol.81, No.3, pp.777 - 788,
2014.
[57]
Zongming Jin,Xiaobao Yu,Siyang Han,Ying Song,Ziqiang Wang,Wen Jia,Baoyong Chi,
A 1.5–1.9GHz phase-locked loop (PLL) frequency synthesizer with AFC and Σ-Δ modulator for Sub-GHz wireless transceiver,
ICSICT 2014,
pp. 1 - 3,
2014.
[58]
Peng Wang,Ziqiang Wang,Chun Zhang,Zhihua Wang,
Data lane design for transmitter of 4.8Gbps serdes in 65nm CMOS,
EDSSC 2014,
pp. 1 - 2,
2014.
[59]
Linghan Wu,Shuai Yuan,Xuqiang Zheng,Ziqiang Wang,Chun Zhang,Zhihua Wang,
A 10Gb/s source-synchronous transmitter in 65nm CMOS technology,
EDSSC 2014,
pp. 1 - 2,
2014.
[60]
Chenlong Hou,Ziqiang Wang,Ke Huang,Chun Zhang,Zhihua Wang,
A 20 GHz PLL for 40 Gbps SerDes application with 4 bit switch-capacitor adaptive controller,
EDSSC 2014,
pp. 1 - 2,
2014.
[61]
Peng Wang,Xuqiang Zheng,Ziqiang Wang,Chun Zhang,Zhihua Wang,
A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS,
EDSSC 2014,
pp. 1 - 2,
2014.
[62]
Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang,
A 10Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65nm CMOS technology,
EDSSC 2014,
pp. 1 - 2,
2014.
[63]
Linghan Wu,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Chun Zhang,Zhihua Wang,
Co-design of 40Gb/s equalizers for wireline transceiver in 65nm CMOS technology,
EDSSC 2014,
pp. 1 - 2,
2014.
[64]
Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang,
A 75mW 50Gbps SerDes Transmitter with Automatic Serializing Time Window Search in 65nm CMOS technology,
CICC 2014,
pp. 1 - 4,
2014.
[65]
Xuan Ma,Ziqiang Wang,
Circuit Design for Transmitter System of 10Gbps SerDes ,
Microelectronics & Computer,
2013.
[66]
Hui Jiang,Ziqiang Wang,Chun Zhang,Hanjun Jiang,Zhihua Wang,
A combined low power SAR capacitance-to-digital analog-to-digital converter for multisensory system,
Analog Integrated Circuits and Signal Processing,
Vol.75, No.2-SI, pp. 311 - 322,
2013.
[67]
Kunzhi Yu,Xuqiang Zheng,Ke Huang,Ma Xuan,Ziqiang Wang,Chun Zhang,Zhihua Wang,
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS,
VLSI-DAT 2013,
pp. 1 - 4,
2013.
[68]
Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Liji Wu,Zhihua Wang,
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology,
ASICON 2013,
pp. 1 – 4,
2013.
[69]
Linghan Wu,Ziqiang Wang,Ke Huang,Shuai Yuan,Xuqiang Zheng,Chun Zhang,Zhihua Wang,
A 10Gb/s analog equalizer in 0.18um CMOS,
ASICON 2013,
pp. 1 - 4,
2013.
[70]
Kaimin Zhou,Ziqiang Wang,Chun Zhang,Zhihua Wang,
A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors,
Chinese Journal of Semiconductors,
Vol.33, No.6,
2012.
[71]
Xijin Zhao,Chun Zhang,Yongming Li,Ziqiang Wang,Yuhui He,
Design of UHF RFID Tag with On-chip Antenna,
Soft Computing in Information Communication Technology 2012,
pp. 77 - 83,
2012.
[72]
Qi Peng,Chun Zhang,Yanhong Song,Ziqiang Wang,Zhihua Wang,
A Low-Cost, Low-Power UHF RFID Reader Transceiver for Mobile Applications,
RFIC 2012,
pp. 243 - 246,
2012.
[73]
Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang,
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS,
MWSCAS 2012,
pp. 932 - 935,
2012.
[74]
Kunzhi Yu,Ziqiang Wang,Xuan Ma,Xuqiang Zheng,Chun Zhang,Zhihua Wang,
A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS,
MWSCAS 2012,
pp. 936 - 939,
2012.
[75]
Hui Jiang,Ziqiang Wang,Liyuan Liu,Chun Zhang,Zhihua Wang,
A Combined Low Power SAR Capacitance-to-Digital/Analog-to-Digital Converter for Multisensory System,
MWSCAS 2012,
pp. 1000 - 1003,
2012.
[76]
Shuai Yuan,Liji Wu,Ziqiang Wang,Xiangmin Zhang,Xuqiang Zheng,
Research on high speed mixed-signal SoC verification based on NanoSim-VCS with a 4.8 Gb/s SerDes transmitter,
ICSICT 2012,
2012.
[77]
Xuguang Sun,Baoyong Chi,Chun Zhang,Ziqiang Wang,Zhihua Wang,
Ultra-high-frequency radio frequency identification reader receiver with 10 dBm input P1 dB and -74 dBm sensitivity in 0.18 μm CMOS,
IET Circuits Devices & Systems,
Vol.5, No.5, pp. 392 - 402,
2011.
[78]
Kaimin Zhou,Ziqiang Wang,Fule Li,Chun Zhang,Zhihua Wang,
A low-power high-linearity symmetrical readout circuit for capacitive sensors,
MWSCAS 2011,
pp. 1 - 4,
2011.
[79]
Linlin Chen,Ziqiang Wang,Chen Jia,Fule Li,Wenhan Hao,Guannan Xu,Chun Zhang,Zhihua Wang,
Zero static power remote control system and the realization of transmitter,
pp. 171 - 175,
2010.
[80]
Xuguang Sun,Baoyong Chi,Chun Zhang,Ziqiang Wang,Zhihua Wang,
A 1.8V 74mW UHF RFID reader receiver with 18.5dBm IIP3 and −77dBm sensitivity in 0.18μm CMOS,
RFIC 2010,
pp. 597 - 600,
2010.
[81]
Linlin Chen,Ziqiang Wang,Chen Jia,Fule Li,Wenhan Hao,Bin Xiao,Chun Zhang,Zhihua Wang,
A RF Remote-Control Transceiver with Zero-Standby Power Based on RFID Technology,
PrimeAsia 2010,
pp. 243 - 246,
2010.
[82]
Ziqiang Wang,Kaimin Zhou,Linlin Chen,Chun Zhang,Zhihua Wang,
Wireless monitoring system using novel capacitive sensor,
ICSICT 2010,
pp. 572 - 574,
2010.
[83]
Tianjia Sun,Xiang Xie,Guolin Li,Yingke Gu,Yangdong Deng,Ziqiang Wang,Zhihua Wang,
An asymmetric resonant coupling wireless power transmission link for Micro-Ball Endoscopy,
EMBC 2010,
pp. 6531 - 6534,
2010.
[84]
Yingke Gu,Xiang Xie,Guolin Li,Tianjia Sun,Qiang Zhang,Ziqiang Wang,Zhihua Wang,
A new system design of the multi-view Micro-Ball endoscopy system,
EMBC 2010,
pp. 6409 - 6412,
2010.
[85]
Yutao Liu,Woogeun Rhee,Ziqiang Wang,Zhihua Wang,
Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit,
APCCAS 2010,
pp. 939 - 942,
2010.
[86]
Kaimin Zhou,Ziqiang Wang,Chun Zhang,Zhihua Wang,
Fully-differential low-offset interface for capacitive sensors,
APCCAS 2010,
pp. 788 - 791,
2010.
[87]
Xi Chen,Ziqiang Wang,Chun Zhang,Zhihua Wang,
Intermediate Frequency Programmable Gain Amplifier with DC Offset Cancellation Loop,
Semiconductor Technology,
Vol.34, No.10, pp. 1041 - 1045,
2009.
[88]
Jingchao Wang,Chun Zhang,Baoyong Chi,Ziqiang Wang,Fule Li,Zhihua Wang,
A Low Cost Integrated Transceiver for Mobile UHF Passive RFID Reader Applications,
Chinese Journal of Semiconductors,
Vol.30, No.9, pp. 095007 - 1 - 5,
2009.
[89]
Qiuling Zhu,Chun Zhang,Xiaohui Wang,Ziqiang Wang,Fule Li,Zhihua Wang,
VLSI Design of Spread Spectrum Encoding Low Power RFID Tag Baseband Processor,
VLSI-DAT 2009,
pp. 191 – 194,
2009.
[90]
Chun Zhang,Wenqiang Zhang,Ziqiang Wang,Jingchao Wang,
A 1.65 mW Direct-Conversion Receiver for UHF RFID Readers,
PrimeAsia 2009,
pp. 109 - 112,
2009.
[91]
Wenqiang Zhang,Ziqiang Wang,Chun Zhang,
A 6.93 μW Wake-Up Circuit for Active RFID Tags,
PrimeAsia 2009,
pp. 452 - 455,
2009.
[92]
Zhongqi Liu,Chun Zhang,Yongming Li,Ziqiang Wang,Zhihua Wang,
A Novel Demodulator for Low Modulation Index RF Signal in Passive UHF RFID Tag,
ISCAS 2009,
pp. 2109 - 2112,
2009.
[93]
Jingchao Wang,Chun Zhang,Baoyong Chi,Ziqiang Wang,Zhihua Wang,
A Fully Integrated CMOS UHF RFID Reader Transceiver for Handheld Applications,
CICC 2009,
pp. 495 - 498,
2009.
[94]
Yingke Gu,Xiang Xie,Ziqiang Wang,Guolin Li,Tianjia Sun,Nan Qi,Chun Zhang,Zhihua Wang,
A New Globularity Capsule Endoscopy System with Multi-Camera,
BioCAS 2009,
pp. 289 - 292,
2009.
[95]
Ziqiang Wang,Baoyong Chi,Zhihua Wang,
Low power, high linearity CMOS programmable gain amplifier,
Journal of Tsinghua University (Science and Technology),
Vol.46, No.4, pp. 519 - 522,
2006.
[96]
Baoyong Chi,Xiaolei Zhu,Ziqiang Wang,Zhihua Wang,
New Implementation of Injection Locked Technique and Its Application to Low Phase Noise Quadrature Oscillators,
Microelectronics Journal,
Vol.37, No.11, pp. 1412 - 1418,
2006.
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Ziqiang Wang,Baoyong Chi,Zhihua Wang,
Microelectronics,
Vol.35, No.6, pp.1,
2005.
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Baoyong Chi,Xiaolei Zhu,Ziqiang Wang,Zhihua Wang,
Quadrature Oscillator with Negative-Resistance Compensated Transformer Couple,
A-SSCC 2005,
pp. 441 - 444,
2005.
[99]
Ziqiang Wang,Baoyong Chi,Min Lin,Shuguang Han,Lu Liu,JinKeYao,Zhihua Wang,
A monolithic CMOS L band DAB receiver,
ASP-DAC 2005,
pp. 1232 - 1235,
2005.
[100]
Ziqiang Wang,Chun Zhang,Zhihua Wang,
Wireless receiver architectures for SOC,
ASICON 2003,
pp. 877 - 881,
2003.
Patents：
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Xiang Xie,Yi Hu,Guolin Li,Ziqiang Wang,Zhihua Wang.
Implementation method and device of neural network approximate multiplier based on Preprocessing:
China,
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Dengjie Wang, Ziqiang Wang, Hong Chen, Chun Zhang, Zhihua Wang.
Dynamic current mode comparator for decision feedback equalizer:
China,
202110549367.9[P].
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Ziqiang Wang, Dengjie Wang, Chen Jia, Hong Chen, Chun Zhang, Zhihua Wang.
Self-adaptive equalization method and system for high-speed serial port transceiver:
China,
201911215963.2[P].
2022-12-30.
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Chen Jia, Ziqiang Wang, Chun Zhang, Lei Quan, Cheng Fang, Yongsheng Yin, Zhihua Wang.
Delay circuit unit weakly related to process corner:
China,
201911214618.7[P].
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Chen Jia, Ziqiang Wang, Chun Zhang, Lei Quan, Yongsheng Yin, Zhihua Wang.
Time delay circuit unit:
China,
201911214623.8[P].
2023-02-10.
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Chen Jia, Ziqiang Wang, Chun Zhang, Lei Quan, Cheng Fang, Yongsheng Yin, Zhihua Wang.
High-speed counting and comparing circuit and method:
China,
201911215985.9[P].
2023-03-24.
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Ben Ma, Chen Jia, Ziqiang Wang, Chun Zhang, Lei Quan, Yongsheng Yin, Zhihua Wang.
Rendering method of delta sub-pixel display panel with different color sequence:
中国,
201910899818.4[P].
2020-10-23.
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Ziqiang Wang, Dengjie Wang, Hong Chen, Chun Zhang, Zhihua Wang.
Hybrid voltage mode and current mode PAM-4 (4-Level Pulse Amplitude Modulation) high-speed driving circuit:
中国,
201910428411.3[P].
2020-12-08.
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Ziqiang Wang, Mao Li, Chun Zhang, Zhihua Wang.
Parallel data bit width conversion circuit for serial interface:
China,
201910243521.2[P].
2020-10-27.
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Jiayi Nie, Chen Jia, Ziqiang Wang, Chun Zhang, Lei Quan, Yongsheng Yin, Zhihua Wang.
A two-sided charge pump with stable output voltage:
China,
201811085204.4[P].
2019-10-08.
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Chen Jia, Ziqiang Wang, Chun Zhang, Lei Quan, Yongsheng Yin, Zhihua Wang.
Display driving circuit, display driving method and display device:
China,
201810752390.6[P].
2020-04-10.
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Shuai Yuan, Wenhuan Luan, Ziqiang Wang, Chun Zhang, Zhihua Wang.
Clock data recovery lock detection circuit adapted to variable bandwidth in high-speed serial communication:
China,
201810592414.6[P].
2021-05-04.
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Ziqiang Wang, Xin Lin, Chun Zhang, Zhihua Wang.
A Multi-band Two-stage Loop Voltage Controlled Oscillator for PLL:
China,
201810388303.3[P].
2020-06-05.
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Shuai Yuan, Ziqiang Wang, Wenhuan Luan, Chun Zhang, Zhihua Wang.
A high speed serial interface receiver front-end circuit compatible with DC / AC coupling:
中国,
201711091775.4[P].
2020-06-05.
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Ziqiang Wang, Wenhuan Luan, Shuai Yuan, Chun Zhang, Zhihua Wang.
On-chip eye-opening monitor circuit based on two-dimensional asymmetrical variable template in high speed serial communication:
China,
201710964551.3[P].
2019-11-22.
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Mao Li, Yuxing Zhou, Dengjie Wang, Shuai Yuan, Zhihua Wang, Ziqiang Wang, Chun Zhang.
A high PSRR low dropout linear regulator:
China,
201710966656.2[P].
2019-02-22.
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Ziqiang Wang, Naiwen Zhou, Fangxu Lv, Chun Zhang, Zhihua Wang, Fule Li.
A transmitter with timing alignment:
China,
201611104171.4[P].
2020-10-27.
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Yajun He, Ziqiang Wang, Woogeun Rhee, Han Liu, Chun Zhang, Zhihua Wang, Fule Li.
A multi-protocol phase-locked loop:
China,
201611104156.X[P].
2018-10-19.
[19]
Fangxu Lv, Ziqiang Wang, Chun Zhang, Zhihua Wang, Fule Li.
A high speed combiner:
China,
201611104765.5[P].
2019-07-12.
[20]
Ziqiang Wang, Chun Zhang, Zhihua Wang.
A high - speed current - mode logic driver:
China,
201611104760.2[P].
2019-09-27.
[21]
Ziqiang Wang, Yuxing Zhou, Chun Zhang, Zhihua Wang, Fule Li.
A Low Dropout Linear Regulator with Analog Circuit Compensation Capacitance:
China,
201611104762.1[P].
2017-12-19.
[22]
Ziqiang Wang, Yuxing Zhou, Chun Zhang, Zhihua Wang, Fule Li.
A Low Dropout Linear Regulator with Digital Circuit Compensation Capacitance:
China,
201611105561.3[P].
2017-12-19.
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Fangxu Lv, Ziqiang Wang, Chun Zhang, Zhihua Wang, Fule Li.
A High Speed Low Power PAM4 Transmitter:
China,
201611104172.9[P].
2018-11-20.
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Weidong Cao, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Fule Li.
A high-speed circuit dynamic latch with pull-up PMOS transistor:
China,
201510497993.2[P].
2017-12-29.
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Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang.
A new high-speed serial interface transmitter:
China,
201410641518.3[P].
2017-07-07.
[26]
Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang.
A new high-speed serial interface transmitter:
China,
201410475671.3[P].
2016-03-30.
[27]
Xuqiang Zheng, Ke Huang, Fule Li, Ziqiang Wang, Chun Zhang, Zhihua Wang.
A clock path front-end amplifier circuit of source synchronous high-speed serial interface:
China,
201310629540.1[P].
2016-08-17.
[28]
Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Liji Wu, Chun Zhang, Zhihua Wang.
A 1/4 rate 4-tap decision feedback equalizer for high-speed serial interface receiving terminal:
China,
201310483312.8[P].
2016-05-18.
[29]
Hui Jiang, Ziqiang Wang, Chun Zhang, Hanjun Jiang, Hong Chen, Zhihua Wang.
Method for imbalance correction by controlling amplitude of pre-amplifier:
China,
201210569383.5[P].
2015-09-02.
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Hui Jiang, Ziqiang Wang, Chun Zhang, Hanjun Jiang, Hong Chen, Zhihua Wang.
Method for imbalance correction by controlling delaying of pre-amplifier:
China,
201210569537.0[P].
2015-08-19.
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Hui Jiang, Ziqiang Wang, Chun Zhang, Songping Mai, Hong Chen, Hanjun Jiang, Zhihua Wang.
Circuit, measuring device and signal measuring method for reducing chopping amplifier output ripple:
China,
201210562798.X[P].
2015-08-19.
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Guannan Xu, Chen Jia, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Hanjun Jiang, Hong Chen, Zhihua Wang.
Buck type switching power supply converter controlled by digital sliding mode variable structure:
China,
201210500397.1[P].
2014-12-10.
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Shijie Hu, Ziqiang Wang, Ke Huang, Xuqiang Zheng, Fule Li, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang.
Clock phase judgment circuit and judgment method in high-speed clock data recovery circuit:
China,
201210478209.X[P].
2015-10-14.
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Chun Zhang, Qi Peng, Shaoxun Shao, Xuguang Sun, Ziqiang Wang, Zhihua Wang.
A mobile integrated with RFID:
China,
201110207900.X[P].
2013-06-12.
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Tianjia Sun, Xiang Xie, Guolin Li, Yingke Gu, Ziqiang Wang, Chun Zhang, Zhihua Wang.
Wireless image acquisition system and method in body cavity:
China,
201110026159.7[P].
2015-10-28.
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Tianjia Sun, Xiang Xie, Guolin Li, Yingke Gu, Ziqiang Wang, Chun Zhang, Zhihua Wang.
Wireless energy transmission system and method:
China,
201010189260.X[P].
2012-06-20.
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Ziqiang Wang, Xiang Xie, Chun Zhang, Yingke Gu, Tianjia Sun, Zhihua Wang.
Positioning method and system of human body endoscope capsule by using electromagnetic wave phase differences:
China,
201010126279.X[P].
2013-06-05.