题目/Title：Design of 80-Gb/s PAM4 Wireline Receiver in 65-nm CMOS Technology

作者/Author：
                        Fangxu Lv,Xuqiang Zheng,Ziqiang Wang,Yajun He,Chun Zhang,Jianye Wang,Zhihua Wang,Hanjun Jiang

会议/Conference：EDSSC 2017

地点/Location：Hsinchu, Taiwan

年份/Issue Date：2017.18-20 Oct.

页码/pages：pp. 1 - 2

摘要/Abstract：
An 80 Gb/s 4-level pulse amplitude modulation (PAM4) wireline receiver is presented in this paper. This receiver adopts quarter rate architecture to improve data rate and reduce power consumption. In order to reduce the complexity of the clock and data recovery (CDR) design, a voltage control oscillator (VCO) based CDR without reference clock is used. Furthermore, four BBPDs are used to sample the edge and data information generated by the middle slicer for extraction the phase error between the data and clock. The receiver is designed in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed PAM4 receiver can work at 80 Gb/s with 235mW consumption.