Title：A high-speed circuit dynamic latch with pull-up PMOS transistor

Country：China

Patent No.：201510497993.2

Legal Status：Authorized

Inventor：Weidong Cao, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Fule Li

Assignee：Tsinghua University

Address：Mailbox No. 82, Beijing 100084

Filing Date：2015-08-13

Issue Date：2017-12-29

The invention relates to the field of circuit design, and in particular relates to a dynamic latch with a pull-up PMOS (P-channel Metal Oxide Semiconductor) transistor of a high-speed circuit. The dynamic latch comprises an NMOS (N-channel Metal Oxide Semiconductor) transistor M0, a pair of NMOS transistor M1 and NMOS transistor M2, a pair of PMOS transistor M3 and PMOS transistor M4 and a pull-up PMOS transistor M6, wherein the NMOS transistor M0 is controlled by a positive edge clock CLKP and has the effect of a tail current source; the NMOS transistor M1 and the NMOS transistor M2 are driven by input data; the PMOS transistor M3 and the PMOS transistor M4 are controlled by a negative edge clock CLKN; and the pull-up PMOS transistor M6 is controlled by the CLKP. According to the invention, the circuit structure of the dynamic latch is improved; one PMOS transistor M6 is additionally arranged over the NMOS transistor M0 as the tail current source; therefore, the performance of the dynamic latch is greatly improved; and the electricity leakage problem of output nodes of the original dynamic latch is effectively solved in the event that the complexity and the power consumption of the circuit are not increased.

Patent Certificate： PDF/Jpg