题目/Title：A 1.25-8.5 Gb/s wide range CDR with locking detector in 40 nm CMOS technology

作者/Author：
                        Wenhuan Luan,Xiangyu Li,Dengjie Wang,Ziqiang Wang,Xin Lin,Mao Li

会议/Conference：EDSSC 2019

地点/Location：Xi'an, China

年份/Issue Date：2019.12-14 June

页码/pages：pp. 1 - 3

摘要/Abstract：
A 1.25-8.5 Gb/s wide range clock and data recovery (CDR) circuit in a multi-protocol SerDes is presented in this paper. The CDR is based on phase interpolator (PI). The local off-chip reference clock is interpolated by the PI to recover the clock at the same frequency as the data rate. Then CDR could retime received data with input jitter and noise in order to export clean waveforms. The circuit is designed in 40nm CMOS technology at 1.1 V supply voltage. Measured results show that bit error rate (BER) is less than 1e-9 and jitter tolerance (JTOL) agrees with template requirements at 1.25-8.5 Gb/s.