Title：Time delay circuit unit
Country：China
Patent No.：201911214623.8
Legal Status：Authorized
Inventor：Chen Jia, Ziqiang Wang, Chun Zhang, Lei Quan, Yongsheng Yin, Zhihua Wang
Assignee：Research Institute of Tsinghua University in Shenzhen
Address：Room A302, Research Institute of Tsinghua University in Shenzhen, the Southern District of the High-tech Industrial Park, Nanshan District, Shenzhen 518057, Guangdong
Filing Date：2019-12-02
Issue Date：2023-02-10
Abstract：
The invention discloses a time delay circuit unit, which comprises six PMOS (P-channel Metal Oxide Semiconductor) tubes, seven NMOS (N-channel Metal Oxide Semiconductor) tubes, a rising edge detectioncircuit and a falling edge detection circuit, on the basis of a traditional time-delay circuit unit, a time-delay compensation circuit is added, so that the time-delay circuit unit weakly related toa process corner is formed. According to the invention, the delay difference caused by different process angles can be offset, the requirements of the system on the delay circuit are met, and the allowance of circuit design can be increased, so that the product yield is improved.
Patent Certificate：
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