【People】

Woogeun Rhee

Biography

Woogeun Rhee received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea, in 1991, the M.S. degree in electrical engineering from the University of California, Los Angeles, in 1993, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 2001.

From 1997 to 2001, he was with Conexant Systems, Newport Beach, CA, where he was a Principal Engineer and mainly involved in the development of low-power low-cost fractional-N synthesizers. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY and worked on clocking area for high-speed I/O serial links, including low-jitter PLLs, clock-and-data recovery circuits, and on-chip testability circuits. In August 2006, he joined the faculty of the Institute of Microelectronics at Tsinghua University, Beijing, China, where he is currently an Associate Professor. His research interests are in low-power, low-cost clock and frequency generation for wireline/wireless systems, and in low-power RF front-end circuits for wireless body area networks (WBAN) and wireless sensor network (WSN) systems. He has 12 U.S. patents issued in clocking and frequency generation areas.

Dr. Rhee has served as an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART–II: EXPRESS BRIEFS and is currently a technical program committee member for IEEE ISSCC, A-SSCC, VLSI-DAT, and CMOS Emerging Technology Workshop. He was the recipient of the IBM Faculty Award in 2007 from IBM Corporation, USA and listed in Marquis Who’s Who in the World (2009-2011).

Publications

Papers：

[1] Bowen Wang, Woogeun Rhee, Zhihua Wang, A 65-nm Sub-10-mW Communication/Ranging Quadrature Uncertain-IF IR-UWB Transceiver With Twin-OOK Modulation, IEEE Journal of Solid-State Circuits, 2023.

[2] Bo Zhou, Yifan L, Zuhang Wang, Chen Wang, Woogeun Rhee, Zhihua Wang, A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking, IEEE Journal of Solid-State Circuits, Vol.PP, No.99, pp.1-12, 2023.

[3] Liqun Feng, Woogeun Rhee, Zhihua Wang, A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter, IEEE Journal of Solid-State Circuits, Vol.PP, No.99, pp.1-12, 2023.

[4] Bowen Wang, Woogeun Rhee, Zhihua Wang, A Quadrature Uncertain-IF IR-UWB Transceiver with Twin-OOK Modulation, ISSCC 2023, pp.1-3, 2023.

[5] Liqun Feng, Woogeun Rhee, Zhihua Wang, A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter, CICC 2023, pp.1-2, 2023.

[6] Yunzhao Nie, Woogeun Rhee, Zhihua Wang, A 17.3mW IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65nm CMOS, ESSCIRC 2023, pp.53-56, 2023.

[7] Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang, A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector, A-SSCC 2023, pp.1-3, 2023.

[8] Yunzhao Nie, Woogeun Rhee, Zhihua Wang, A 405ps/20% Delay Range, 7.4mW/ns BPF-Based Delay Cell with ISI Mitigation for 7.5-8.5GHz IR-UWB Beamforming Receivers, ICTA 2023, pp.19-20, 2023.

[9] Bowen Wang, Haixin Song, Woogeun Rhee, Zhihua Wang, Overview of Ultra-Wideband Transceivers—System Architectures and Applications, Tsinghua Science and Technology, Vol.27, No.3, pp.481-494, 2022.

[10] Liqun Feng, Woogeun Rhee, Zhihua Wang, A Quantization Noise Reduction Method for Delta-Sigma Fractional-N PLLs Using Cascaded Injection-Locked Oscillators, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69, No.5, pp.2448-2452, 2022.

[11] Su Han, Bowen Wang, Woogeun Rhee, Zhihua Wang, An 8GHz Communication/Ranging IR-UWB Transmitter with Asymmetric Pulse Shaping and Frequency Hopping for Fine Ranging and Enhanced Link Margin, ISCAS 2022, pp.757-760, 2022.

[12] Zixiang Wan, Xinyu Xu, Woogeun Rhee, Zhihua Wang, A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS, ICTA 2022, pp.76-77, 2022.

[13] Luhua Lin, Bowen Wang, Woogeun Rhee, Zhihua Wang, An Analog-Assisted Digital LDO with 0.37mV Output Ripple and 5500x Load Current Range in 180nm CMOS, ICTA 2022, pp.106-107, 2022.

[14] Jiahao Zhao, Xuansheng Ji, Su Han, Ziwei Wang, Woogeun Rhee, Zhihua Wang, A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction, ICTA 2022, pp.74-75, 2022.

[15] Bowen Wang, Haixin Song, Woogeun Rhee, Zhihua Wang, A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection, CICC 2022, pp.1-2, 2022.

[16] Bowen Wang, Cong Ding, Yunzhao Nie, Woogeun Rhee, Zhihua Wang, A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection, CICC 2022, pp.1-2, 2022.

[17] Bowen Wang,Haixin Song,Woogeun Rhee,Zhihua Wang, Overview of ultra-wideband transceivers—system architectures and applications, Tsinghua Science and Technology, Vol.27, No.3, pp.481-494, 2021.

[18] Xinyu Xu,Zixiang Wan,Woogeun Rhee,Zhihua Wang, A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.68, No.9, pp.3611-3620, 2021.

[19] Meng Ni,Xiao Wang,Fule Li,Woogeun Rhee,Zhihua Wang, A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.PP, No.99, pp.1-14, 2021.

[20] Cong Ding,Bowen Wang,Haxin Song,Woogeun Rhee,Zhihua Wang, A 3.5-GHz 0.24-nJ/b 100-Mb/s Fully Balanced FSK Receiver With Sideband Energy Detection, IEEE Solid-State Circuits Letters, Vol.4, pp.26-29, 2021.

[21] Zixiang Wan,Woogeun Rhee,Zhihua Wang, Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops, ISCAS 2021, pp.1-4, 2021.

[22] Jiahao Zhao,Yining Zhang,Kunnong Zeng,Woogeun Rhee,Zhihua Wang, A 2.4-GHz Crystal-Less GFSK Receiver Using an Auxiliary Multiphase BBPLL for Digital Output Demodulation With Enhanced Frequency Scaling, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.PP, No.99, pp. 1 - 1, 2020.

[23] Xuqiang Zheng,Fangxu Lv,Lei Zhou,Danyu Wu,Jin Wu,Chun Zhang,Woogeun Rhee,Xinyu Liu, Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators, IEEE Journal of Solid-State Circuits, Vol.55, No.6, pp. 1651 - 1664, 2020.

[24] Haixin Song,Dang Liu,Yining Zhang,Woogeun Rhee,Zhihua Wang, A 6.5–8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efficiency and ΔΣ Energy Detection, IEEE Journal of Solid-State Circuits, Vol.55, No.2, pp. 219 - 232, 2020.

[25] Xiaohua Huang,Bowen Wang,Woogeun Rhee,Zhihua Wang, A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter, VLSI-DAT 2020, pp. 1 - 2, 2020.

[26] Bowen Wang,Woogeun Rhee,Zhihua Wang, A Sub-10fs FOM, 5000x Load Driving Capacity and 5mV Output Ripple Digital LDO with Dual-Mode Nonlinear Voltage Detector and Dead-Zone Charge Pump Loop, RFIC 2020, pp. 315 - 318, 2020.

[27] Yuguang Liu,Woogeun Rhee,Zhihua Wang, A 1Mb/s 2.86% EVM GFSK Modulator Based on ΔΣ BB-DPLL without Background Digital Calibration, RFIC 2020, pp. 7 - 10, 2020.

[28] Meng Ni,Xiao Wang,Zhe Zhou,Yang Ding,Fule Li,Woogeun Rhee,Zhihua Wang, A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC, MWSCAS 2020, pp. 345 - 348, 2020.

[29] Meng Ni,Xiao Wang,Zhe Zhou,Yang Ding,Fule Li,Woogeun Rhee,Zhihua Wang, A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique, MWSCAS 2020, pp. 341 - 344, 2020.

[30] Xinyu Xu,Woogeun Rhee,Zhihua Wang, A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation, ISCAS 2020, pp. 1 - 4, 2020.

[31] Zixiang Wan,Woogeun Rhee,Zhihua Wang, A Nonlinearity-Calibration-Free Reconfigurable ADPLL for General Purpose Frequency Modulation, ICTA 2020, pp.19-20, 2020.

[32] Haixin Song,Woogeun Rhee,Zhihua Wang, A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity, CICC 2020, pp. 1 - 4, 2020.

[33] Zhendong Ding,Xinyu Xu,Haixin Song,Woogeun Rhee,Zhihua Wang, Flash ADC-based digital LDO with non-linear decoder and exponential-ratio array, Electronics Letters, Vol.55, No.10, pp. 585 - 587, 2019.

[34] Yining Zhang,Haixin Song,Ranran Zhou,Woogeun Rhee,Zhihua Wang, A Capacitor-less Ripple-less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.66, No.1, pp. 36 - 40, 2019.

[35] Haixin Song,Dang Liu,Yining Zhang,Woogeun Rhee,Zhihua Wang, A 6.5-8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efficiency and ΔΣ Energy Detection, IEEE Journal of Solid-State Circuits, Vol.PP, No.99, pp. 1 - 14, 2019.

[36] Yining Zhang,Meng Ni,Xiaohua Huang,Woogeun Rhee,Zhihua Wang, A 3.7-mW 2.4-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation, IEEE Journal of Solid-State Circuits, Vol.54, No.2, pp. 336 - 345, 2019.

[37] Yining Zhang,Jiahao Zhao,Woogeun Rhee,Zhihua Wang, Design and Analysis of Data-Pattern-Insensitive Phase-Tracking Receivers with Fully-Balanced FSK Modulation, VLSI-DAT 2019, pp. 1 - 4, 2019.

[38] Yuguang Liu,Haixin Song,Kunnong Zeng,Woogeun Rhee,Zhihua Wang, A 9mW 6-9GHz 2.5Gb/s Proximity Transmitter with Combined OOK/BPSK Modulation for Low Power Mobile Connectivity, VLSI-DAT 2019, pp. 1 - 4, 2019.

[39] Xiaohua Huang,Kunnong Zeng,Woogeun Rhee,Zhihua Wang, A Noise and Spur Reduction Technique for ΔΣ Fractional-N Bang-Bang PLLs with Embedded Phase Domain Filtering, ISCAS 2019, pp. 1 - 4, 2019.

[40] Cong Ding,Woogeun Rhee,Zhihua Wang, A Gaussian-Filtered Fully-Balanced FSK Modulator with Integer-N PLL Based 1+-Point Modulation, ISCAS 2019, pp. 1 - 4, 2019.

[41] Xinyu Xu,Woogeun Rhee,Zhihua Wang, Enhanced FIR-embedded noise reduction method with hybrid phase detection for semidigital fractional-N phase-locked loops, ICTA 2019, pp. 94 - 95, 2019.

[42] Kunnong Zeng,Woogeun Rhee,Zhihua Wang, A BBPLL-Based Demodulator with Multiphase and Feedforward Linearization Methods for Phase-Tracking Receivers, EDSSC 2019, pp. 1 - 3, 2019.

[43] Xiaohua Huang,Kunnong Zeng,Yuguang Liu,Woogeun Rhee,Taeik Kim,Zhihua Wang, A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL, CICC 2019, pp. 1 - 4, 2019.

[44] Cong Ding,Haixin Song,Woogeun Rhee,Zhihua Wang, A 100Mb/s 3.5GHz Fully-Balanced BFOOK Modulator Based on Integer-N Hyrbrid PLL, A-SSCC 2019, pp. 291 - 294, 2019.

[45] Yanshu Guo,Hanjun Jiang,Heng Liu,Zhaoyang Weng,Woogeun Rhee,Chun Zhang,Zhihua Wang, A 120 pJ/bit ΔΣ -Based 2.4-GHz Transmitter Using FIR-Embedded Digital Power Amplifier, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.65, No.12, pp. 1854 - 1858, 2018.

[46] Fei Chen,Woogeun Rhee,Zhihua Wang, A 5-mW 750-kb/s Noninvasive Transceiver for Around-the-Head Audio Applications, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.65, No.2, pp. 196 - 200, 2018.

[47] Xiaohua Huang,Dang Liu,Woogeun Rhee,Zhihua Wang, A 1-GHz 1.6-mW Auto-Calibrated Bit Slicer for Energy/Envelope Detection Receivers, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.65, No.5, pp. 587 - 591, 2018.

[48] Zhaoyang Weng,Hanjun Jiang,Jingjing Dong,Yang Li,Jingyi Zheng,Yiyu Shen,Fule Li,Woogeun Rhee,Zhihua Wang, 400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.65, No.2, pp. 745 - 757, 2018.

[49] Jianfu Lin,Zheng Song,Nan Qi,Woogeun Rhee,Zhihua Wang,Baoyong Chi, A 77-GHz Mixed-Mode FMCW Signal Generator Based on Bang-Bang Phase Detector, IEEE Journal of Solid-State Circuits, Vol.53, No.10, pp. 2850 - 2863, 2018.

[50] Xiaohua Huang,Han Liu,Woogeun Rhee,Zhihua Wang, A DS DPLL with 1b TDC, 4b DTC and 8-Tap FIR Filter For Low-Voltage Clock Generation/Modulation Systems, VLSI-DAT 2018, pp. 1 - 2, 2018.

[51] Xiaohua Huang,Han Liu,Woogeun Rhee,Zhihua Wang, A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems, VLSI-DAT 2018, pp. 1 - 4, 2018.

[52] Zhendong Ding,Woogeun Rhee,Zhihua Wang, A VCO-dedicated digital LDO with multi-comparator coarse loop and 1-bit ΔΣ fine loop for robust frequency generation, IWS 2018, pp. 1 - 4, 2018.

[53] Yuguang Liu,Haixin Song,Woogeun Rhee,Zhihua Wang, A 13.5mW 4Gb/s Filter-less UWB Transmitter for High Data Rate Mobile Applications, ICSICT 2018, pp. 1 - 3, 2018.

[54] Dang Liu,Xiaohua Huang,Zhendong Ding,Haixin Song,Woogeun Rhee,Zhihua Wang, A 26.6mW 1Gb/s dual-antenna wideband receiver with auto beam steering for secure proximity communications, CICC 2018, 2018.

[55] Haixin Song,Dang Liu,Woogeun Rhee,Zhihua Wang, A 6-8GHZ 200MHz Bandwidth 9-Channel VWB Transceiver with 8 Frequency-Hopping Subbands, A-SSCC 2018, pp. 295 - 298, 2018.

[56] Yining Zhang,Ranran Zhou,Woogeun Rhee,Zhihua Wang, A 1.9-mW 750-kb/s 2.4-GHz F-OOK Transmitter With Symmetric FM Template and High-Point Modulation PLL, Journal of Solid-State Circuits, Vol.52, No.10, pp.2627 - 2635, 2017.

[57] Xiaoyong Li,Sitao Lv,Woogeun Rhee,Wen Jia,Zhihua Wang, 20-Mb/s GFSK Modulator Based on 3.6-GHz Hybrid PLL With 3-b DCO Nonlinearity Calibration and Independent Delay Mismatch Control, IEEE Transactions on Microwave Theory and Techniques, Vol.65, No.7, pp. 2387 - 2398, 2017.

[58] Xican Chen,Yiyu Shen,Zhicheng Wang,Woogeun Rhee,Zhihua Wang, A 17 mW 3-to-5 GHz Duty-Cycled Vital Sign Detection Radar Transceiver With Frequency Hopping and Time-Domain Oversampling, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.64, No.4, pp. 969 - 980, 2017.

[59] Dang Liu,Xuwen Ni,Ranran Zhou,Woogeun Rhee,Zhihua Wang, A 0.42-mW 1-Mb/s 3- to 4-GHz Transceiver in 0.18- μm CMOS With Flexible Efficiency, Bandwidth, and Distance Control for IoT Applications, IEEE Journal of Solid-State Circuits, Vol.52, No.6, pp. 1479 - 1494, 2017.

[60] Woogeun Rhee,Dang Liu,Yining Zhang,Zhihua Wang, Energy-efficient proprietary transceivers for IoT and smartphone-based WPAN, RFIT 2017, pp. 40 - 42, 2017.

[61] Han Liu,Sitao Lv,Xiaohua Huang,Woogeun Rhee,Zhihua Wang, A fractional-NBB-DPLL with auto-tuned DTC and FIR filter for noise and spur reduction, RFIT 2017, pp. 238 - 240, 2017.

[62] Yudong Zhang,Xiaofeng Liu,Woogeun Rhee,Hanjun Jiang,Zhihua Wang, A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS, ISCAS 2017, pp. 1 - 4, 2017.

[63] Ranran Zhou,Yining Zhang,Woogeun Rhee,Zhihua Wang, An Energy/Bandwidth/Area Efficient Frequency-Domain OOK Transmitter with Phase Rotated Modulation, ISCAS 2017, pp. 1 - 4, 2017.

[64] Yining Zhang,Ranran Zhou,Woogeun Rhee,Zhihua Wang, A 6.1mW 5Mb/s 2.4GHz transceiver with F-OOK modulation for high bandwidth and energy efficiencies, CICC 2017, pp. 1 - 4, 2017.

[65] Xiaofeng Liu,Dang Liu,Woogeun Rhee,Zhihua Wang, A Multiphase Clock Generation for UWB Transceiver, Microelectronics & Computer, Vol.33, No.11, pp. 87-90+94, 2016.

[66] Hanjun Jiang,Zhaoyang Weng,Yang Li,Jingjing Dong,Woogeun Rhee,Zhihua Wang, A 10 Mbps 0.3 nJ/bit OQPSK transceiver IC for 400-450 MHz medical telemetry, Electronics Letters, Vol.52, No.22, pp. 1830 - 1832, 2016.

[67] Hanjun Jiang,Zhaoyang Weng,Yang Li,Jingjing Dong,Woogeun Rhee,Zhihua Wang, 10 Mbps 0.3 nJ/bit OQPSK transceiver IC for 400–450 MHz medical telemetry, Electronics Letters, Vol.52, No.22, pp. 1830-1832, 2016.

[68] Haixin Song,Woogeun Rhee,Inbo Shim,Zhihua Wang, Digital LDO with 1-bit ΔΣ modulation for low-voltage clock generation systems, Electronics Letters, Vol.52, No.25, pp. 2034 - 2036, 2016.

[69] Sitao Lv,Ni Xu,Woogeun Rhee,Zhihua Wang, A Hybrid Frequency/Phase-Locked Loop for Versatile Clock Generation with Wide Reference Frequency Range, VLSI-DAT 2016, pp. 1 - 4, 2016.

[70] Yining Zhang,Xuwen Ni,Woogeun Rhee,Zhihua Wang, A 1.8mW 2Mb/s Chirp-UWB Transceiver with Burst-Mode Transmission and Slope-Based Detection, RFIT 2016, pp. 1 - 3, 2016.

[71] Xuwen Ni,Woogeun Rhee,Zhihua Wang, A 0.3mW 1Mb/s High Security Proximity UWB Transmitter with Frequency/Time-Domain Scrambling, RFIT 2016, pp. 1 - 3, 2016.

[72] Xuwen Ni,Yining Zhang,Woogeun Rhee,Wen Jia,Zhihua Wang, A 0.5mW 1Mb/s Multi-Channel Chirp-UWB Transmitter with Burst-Mode Transmission and Optimized Digital Gradient, IWS 2016, pp. 1 - 4, 2016.

[73] Han Liu,Woogeun Rhee,Zhihua Wang, A 10.3mW 13.6GHz Phase-Locked Loop with Boosted Gm Two-Stage Ring VCO, ICSICT 2016, 2016.

[74] Ranran Zhou,Yining Zhang,Woogeun Rhee,Zhihua Wang, 2.4GHz 20Mb/s FSK Receiver Front-End and Transmitter Modulation PLL Design for Energy-Efficient Short-Range Communication, EDSSC 2016, 2016.

[75] Yining Zhang,Ranran Zhou,Woogeun Rhee,Zhihua Wang, A 1.9mW 750kb/s 2.4GHz F-OOK transmitter with symmetric FM template and high-point modulation PLL, A-SSCC 2016, pp. 277 - 280, 2016.

[76] Yudong Zhang,Woogeun Rhee,Taeik Kim,Hojin Park,Zhihua Wang, A 0.35–0.5-V 18–152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.62, No.8, pp. 736 - 740, 2015.

[77] Ni Xu,Woogeun Rhee,Zhihua Wang, A 2 GHz 2 Mb/s Semi-Digital 2+-Point Modulator With Separate FIR-Embedded 1-Bit DCO Modulation in 0.18 μm CMOS, IEEE Microwave and Wireless Components Letters, Vol.25, No.4, pp. 253 - 255, 2015.

[78] Shuli Geng,Dang Liu,Yanfeng Li,Huiying Zhuo,Woogeun Rhee,Zhihua Wang, A 13.3 mW 500 Mb/s IR-UWB Transceiver With Link Margin Enhancement Technique for Meter-Range Communications, IEEE Journal of Solid-State Circuits, Vol.50, No.3, pp. 669 - 678, 2015.

[79] Xican Chen,Woogeun Rhee,Zhihua Wang, Low power sensor design for IoT and mobile healthcare applications, China Communications, Vol.12, No.5, pp. 42 - 54, 2015.

[80] Yanfeng Li,Yutao Liu,Woogeun Rhee,Zhihua Wang, A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator, VLSI-DAT 2015, pp. 1 - 4, 2015.

[81] Yudong Zhang,Woogeun Rhee,Zhihua Wang,Taeik Kim,Hojin Park, A 0.55V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS, RFIT 2015, pp. 190 - 192, 2015.

[82] Ni Xu,Sitao Lv,Woogeun Rhee,Zhihua Wang, A digital-intensive F/PLL-based two-point modulator with a constant-gain DCO for linear FMCW generation, RFIT 2015, pp. 193 - 195, 2015.

[83] Heng Liu,Hanjun Jiang,Yiyu Shen,Woogeun Rhee,Zhihua Wang, A Delta-Sigma-Based Transmitter Utilizing FIR Embedded Digital Power Amplifiers, MWSCAS 2015, 2015.

[84] Xiaoyong Li,Sitao Lv,Xiaofeng Liu,Ni Xu,Woogeun Rhee,Wen Jia,Zhihua Wang, A 10 Mb/s Hybrid Two-Point Modulator with Front-End Phase Selection and Dual-Path DCO Modulation, IWS 2015, pp. 1 - 4, 2015.

[85] Xiaoyong Li,Woogeun Rhee,Wen Jia,Zhihua Wang, A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path, ISCAS 2015, pp. 894 - 897, 2015.

[86] Yiyu Shen,Woogeun Rhee,Zhihua Wang, A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters, ISCAS 2015, pp. 662 - 665, 2015.

[87] Chao Yang,Shaoquan Gao,Jingjing Dong,Hanjun Jiang,Woogeun Rhee,Zhihua Wang, A 2.4 GHz two-point Δ-Σ modulator with gain calibration and AFC for WPAN/BAN applications, ASICON 2015, pp. 1 - 4, 2015.

[88] Yutao Liu,Woogeun Rhee,Zhihua Wang, Microelectronics, Vol.44, No.3, pp.1, 2014.

[89] Xican Chen,Wei Zhang,Woogeun Rhee,Zhihua Wang, A ΔΣ-TDC-Based Beamforming Method for Vital Sign Detection Radar Systems, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.61, No.12, pp. 932 - 936, 2014.

[90] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Ni Xu,Woogeun Rhee,Liji Wu,Chun Zhang, A 4.8-mW/Gb/s 9.6-Gb/s 5+1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.61, No.4, pp. 209 - 213, 2014.

[91] Yutao Liu,Yizhi Han,Woogeun Rhee,Tae-Young Oh,Zhihua Wang, A PSRR Enhancing Method for GRO TDC Based Clock Generation Systems, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.61, No.3, pp. 680 - 688, 2014.

[92] Ni Xu,Woogeun Rhee,Zhihua Wang, A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation, IEEE Journal of Solid-State Circuits, Vol.49, No.10, pp. 2172 - 2186, 2014.

[93] Wei Zhang,Yizhi Han,Fei Chen,Bo Zhou,Xican Chen,Woogeun Rhee,Zhihua Wang, A 3.5–4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC, VLSI-DAT 2014, pp. 1 - 4, 2014.

[94] Huiying Zhuo,Yu Li,Woogeun Rhee,Zhihua Wang, A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS, VLSI-DAT 2014, pp. 1 - 4, 2014.

[95] Yu Li,Fei Chen,Dang Liu,Xiaoyong Li,Yang Li,Yudong Zhang,Zhicheng Wang,Woogeun Rhee,Zhihua Wang, A 1.6Mb/s 3.75–4.25GHz chirp-UWB transceiver with enhanced spectral efficiency in 0.18μm CMOS, RFIT 2014, pp. 1 – 3, 2014.

[96] Fei Chen,Yu Li,Dang Liu,Woogeun Rhee,Jongjin Kim,Dongwook Kim,Zhihua Wang, A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability, ISSCC 2014, pp. 162 - 163, 2014.

[97] Shuli Geng,Dang Liu,Yanfeng Li,Huiying Zhuo,Woogeun Rhee,Zhihua Wang, A 13.3mW 500Mb/s IR-UWB Transceiver with Link-Margin Enhancement Technique for Meter-Range Communications, ISSCC 2014, pp. 160 - 161, 2014.

[98] Yanfeng Li,Ni Xu,Woogeun Rhee,Zhihua Wang, A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL, ISCAS 2014, pp. 1440 - 1443, 2014.

[99] Dang Liu,Shuli Geng,Woogeun Rhee,Zhihua Wang, A high efficiency robust IR-UWB receiver design for high data rate CM-range communications, ISCAS 2014, pp. 1901 - 1904, 2014.

[100] Yiyu Shen,Xican Chen,Woogeun Rhee,Zhihua Wang, A second-order multi-bit ΔΣ TDC for high resolution IR-UWB radar systems, IEEE-IWS 2014, pp. 1 - 4, 2014.

[101] Yu Li,Fei Chen,Woogeun Rhee,Zhihua Wang, A chirp-UWB transceiver with embedded bulk PPM for energy efficient data transmission, IEEE-IWS 2014, pp. 1 - 4, 2014.

[102] Zhicheng Wang,Xican Chen,Yiyu Shen,Woogeun Rhee,Zhihua Wang, A 2.5–4.5 GHz CMOS fast settling PLL for IR-UWB radar applications, ICSICT 2014, pp. 1 - 3, 2014.

[103] Zhicheng Wang,Xican Chen,Yiyu Shen,Woogeun Rhee,Zhihua Wang, A 3.1–4.8-GHz delay-line-based frequency-hopping IR-UWB transmitter in 65-NM CMOS technology, ICSICT 2014, pp. 1 - 3, 2014.

[104] Yang Li,Ni Xu,Yining Zhang,Wooguen Rhee,Sanghoon Kang,Zhihua Wang, A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications, A-SSCC 2014, pp. 261 - 264 , 2014.

[105] Bo Zhou,Woogeun Rhee,Dongwook Kim,Zhihua Wang, Reconfigurable FM-UWB transmitter design for robust short range communications, Telecommunication Systems, Vol.52, No.2, pp. 1133 - 1144, 2013.

[106] Woogeun Rhee,Ni Xu,Bo Zhou,Zhihua Wang, Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design, Journal of Semiconductor Technology and Science, Vol.13, No.2, pp. 170 - 183, 2013.

[107] Fei Chen,Wei Zhang,Woogeun Rhee,Jongjin Kim,Dongwook Kim,Zhihua Wang, A 3.8-mW 3.5–4-GHz Regenerative FM-UWB Receiver With Enhanced Linearity by Utilizing a Wideband LNA and Dual Bandpass Filters, IEEE Transactions on Microwave Theory and Techniques, Vol.61, No.9, pp. 3350 - 3359, 2013.

[108] Wei Zhang,Xican Chen,Fei Chen,Woogeun Rhee,Zhihua Wang, A Phase-Domain Delta Sigma Ranging Method for FMCW Radar Receivers, IEEE Transactions on Circuits and Systems II-Express Briefs, Vol.60, No.9, pp. 537 - 541, 2013.

[109] Bo Zhou,Fei Chen,Woogeun Rhee,Zhihua Wang, A Reconfigurable FM-UWB Transceiver for Short-Range Wireless Communications, IEEE Microwave and Wireless Components Letters, Vol.23, No.7, pp. 371 - 373, 2013.

[110] Y. Han,D. Lin,Shuli Geng,Ni Xu,Woogeun Rhee,T-Y Oh,Zhihua Wang, All-digital PLL with ΔΣ DLL embedded TDC, Electronics Letters, Vol.49, No.2, pp. 93 - 94, 2013.

[111] Hang Lv,Bo Zhou,Dang Liu,Woogeun Rhee,Yongming Li,Zhihua Wang, A 5.2–11.8MHz octa-phase relaxation oscillator for 8-PSK FM-UWB transceiver systems, VLSI-DAT 2013, pp. 1 - 4, 2013.

[112] Dang Liu,Fei Chen,Woogeun Rhee,Zhihua Wang, An FM-UWB transceiver with M-PSK subcarrier modulation and regenerative FM demodulation, MWSCAS 2013, pp. 936 – 939, 2013.

[113] Shuli Geng,Ni Xu,Jun Li,Xueyi Yu,Woogeun Rhee,Zhihua Wang, A PLL/DLL Based CDR with Delta-Sigma Frequency Tracking and Low Algorithmic Jitter Generation, ISCAS 2013, pp. 1179 - 1182, 2013.

[114] Fei Chen,Yu Li,Deyuan Lin,Huiying Zhuo,Woogeun Rhee,Jongjin Kim,Dongwook Kim,Zhihua Wang, A 1.14mW 750kb/s FM-UWB transmitter with 8-FSK subcarrier modulation, CICC 2013, pp. 1 - 4, 2013.

[115] Bo Zhou,Jian Qiao,Rui He,Jinghui Liu,Wei Zhang,Hang Lv,Woogeun Rhee,Yongming Li,Zhihua Wang, A Gated FM-UWB System With Data-Driven Front-End Power Control, IEEE Transactions on Circuits and Systems I-Regular Papers, Vol.59, No.6, pp. 1348 - 1358, 2012.

[116] Nan Qi,Yang Xu,Baoyong Chi,Yang Xu,Xiaobao Yu,Xing Zhang,Ni Xu,Patrick Chiang,Woogeun Rhee, Zhihua Wang, A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration, IEEE Transactions on Circuits and Systems -I: Regular papers, Vol.59, No.8, pp. 1720 - 1732, 2012.

[117] Yuanfeng Sun,Zhuo Zhang,Ni Xu,Min Wang,Woogeun Rhee,Tae-Young Oh,Zhihua Wang, A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control, IEEE Microwave and Wireless Components Letters, Vol.22, No.12, pp. 654 - 656, 2012.

[118] Fei Chen,Wei Zhang,Woogeun Rhee,Jongjin Kim,Dongwook Kim,Zhihua Wang, A 3.8mW, 3.5–4GHz regenerative FM-UWB receiver with enhanced linearity by utilizing a wideband LNA and dual bandpass filters, RFIT 2012, pp. 150 - 152, 2012.

[119] Yuanfeng Sun,Jun Li,Zhuo Zhang,Min Wang,Ni Xu,Hang Lv,Woogeun Rhee,Yongming Li,Zhihua Wang, A 2.74–5.37GHz boosted-gain type-I PLL with <15% loop filter area, RFIC 2012, pp. 181 - 184, 2012.

[120] Yizhi Han,Woogeun Rhee,Zhihua Wang, A PVT-Insensitive Self-Dithered TDC Design by Utilizing a DS DLL, MWSCAS 2012, pp. 542 - 545, 2012.

[121] Shuli Geng,Woogeun Rhee,Zhihua Wang, A pulse-shaped power amplifier with dynamic bias switching for IR-UWB transmitters, ISCAS 2012, pp. 2529 - 2532, 2012.

[122] Wei Zhang,Woogeun Rhee,Zhihua Wang, A ΔΣ IR-UWB Radar with Sub-mm Ranging Capability for Human Body Monitoring Systems, ISCAS 2012, pp. 1315 - 1318, 2012.

[123] Ke Huang,Chen Jia,Xuqiang Zheng,Ni Xu,Chun Zhang,Woogeun Rhee,Zhihua Wang, A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology, ISCAS 2012, pp. 313 - 316, 2012.

[124] Deyuan Lin,Ni Xu,Woogeun Rhee,Zhihua Wang, An 11.7–17.2GHz digitally-controlled oscillator in 65nm CMOS for high-band UWB applications, ICSICT 2012, pp. 1 - 3, 2012.

[125] Yizhi Han,Woogeun Rhee,Zhihua Wang, Design and Analysis of a Robust All-Digital Clock Generation System with a DLL-based TDC, CECNet 2012, pp. 3152 - 3156, 2012.

[126] Shuli Geng,Xican Chen,Woogeun Rhee,Jongjin Kim,Dongwook Kim,Zhihua Wang, A Power-Efficient All-Digital IR-UWB Transmitter with Configurable Pulse Shaping by Utilizing a Digital Amplitude Modulation Technique, A-SSCC 2012, pp. 85 - 88, 2012.

[127] Zhuo Zhang,Xican Chen,Woogeun Rhee,Zhihua Wang, A Cint-less type-II PLL with ΔΣ DAC based frequency acquisition and reduced quantization noise, A-SSCC 2012, pp. 301 - 304, 2012.

[128] Ni Xu,Woogeun Rhee,Zhihua Wang, Semidigital PLL design for low-cost low-power clock generation, Journal of Electrical and Computer Engineering, Vol.2011, pp. 1 - 9, 2011.

[129] Yuanfeng Sun,Jian Qiao,Xueyi Yu,Woogeun Rhee,Byeong-Ha Park,Zhihua Wang, A continuously tunable hybrid LC-VCO PLL with mixed-mode dual-path control and bi-level delta-sigma modulated coarse tuning, IEEE Transactions on Circuits and Systems I-Regular Papers, Vol.58, No.9, pp. 2149 - 2158, 2011.

[130] Bo Zhou,Woogeun Rhee,Zhihua Wang, Relaxation Oscillator with Quadrature Triangular and Square Waveform Generation, Electronics Letters, Vol.47, No.13, pp. 779 - 780, 2011.

[131] Bo Zhou,Woogeun Rhee,Zhihua Wang, Reconfigurable FM-UWB Transmitter, Electronics Letters, Vol.47, No.10, pp. 628 - 629, 2011.

[132] Jun Li,Bo Zhou,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, Reconfigurable, Spectrally Efficient, High Data Rate IR-UWB Transmitter Design Using a Δ–Σ PLL Driven ILO and a 7-Tap FIR Filter, VLSI-DAT 2011, pp. 1 - 4, 2011.

[133] Woogeun Rhee,Bo Zhou,Zhihua Wang, Fractional-N frequency synthesis: Overview and design perspectives, RFIT 2011, pp. 125 - 128, 2011.

[134] Bo Zhou,Hang Lv,Min Wang,Jinghui Liu,Woogeun Rhee,Yongming Li,Dongwook Kim,Zhihua Wang, A 1Mb/s 3.2–4.4GHz reconfigurable FM-UWB transmitter in 0.18μm CMOS, RFIC 2011, pp. 1 - 4, 2011.

[135] Ni Xu,Zhuo Zhang,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, Technology-Friendly Phase-Locked Loops, MWSCAS 2011, pp. 1 - 4, 2011.

[136] Hang Lv,Bo Zhou,Woogeun Rhee,Yongming Li,Zhihua Wang, A Relaxation Oscillator with Multi-Phase Triangular Waveform Generation, ISCAS 2011, pp. 2837 - 2840, 2011.

[137] Zhuo Zhang,Woogeun Rhee,Zhihua Wang, A Wide-Tuning Quasi-Type-I PLL with Voltage-Mode Frequency Acquisition Aid, ISCAS 2011, pp. 474 - 477, 2011.

[138] Min Wang,Bo Zhou,Woogeun Rhee,Zhihua Wang, Continuously Auto-Tuned and Self-Ranged Dual-path PLL design with Hybrid AFC, ICICDT 2011, pp. 1 - 4, 2011.

[139] Yuanfeng Sun,Xueyi Yu,Woogeun Rhee,Sangsoo Ko,Wooseung Choo,Byeong-Ha Park,Zhihua Wang, Dual-Path LC VCO Design With Partitioned Coarse-Tuning Control in 65 nm CMOS, IEEE Microwave and Wireless Components Letters, Vol.20, No.3, pp. 169 - 171 , 2010.

[140] Yuanfeng Sun,Xueyi Yu,Woogeun Rhee,Dawn Wang,Zhihua Wang, A Fast Settling Dual-Path Fractional-N PLL With Hybrid-Mode Dynamic Bandwidth Control, IEEE Microwave and Wireless Components Letters, Vol.20, No.8, pp. 462 - 464, 2010.

[141] Bo Zhou,Jian Qiao,Woogeun Rhee,Zhihua Wang, Relaxation Oscillator with Quadrature Triangular Waveform Generation, Electronic Letters, pp. 1 - 4, 2010.

[142] Xueyi Yu,Chengwen Liu,Woogeun Rhee,Zhihua Wang, Digitally controlled oscillator with FIR-embedded ΔΣ modulation, Electronic Letters, pp. 97 - 100, 2010.

[143] Xueyi Yu,Jian Qiao,Woogeun Rhee,Joon-Young Park,Kyongsu Lee,Zhihua Wang, A Semi-Digital Cascaded CDR With Fast Phase Acquisition and Adaptive Resolution Control, VLSI-DAT 2010, pp. 307 - 310, 2010.

[144] Yuanfeng Sun,Xueyi Yu,Woogeun Rhee,Sangsoo Ko,Wooseung Choo,Byeong-Ha Park,Zhihua Wang, Low-Noise Fractional-N PLL Design with Mixed-Mode Triple-Input LC VCO in 65nm CMOS, RFIC 2010, pp. 61 - 64, 2010.

[145] Jun Li,Ni Xu,Woogeun Rhee,Zhihua Wang, A -131dBc@1M PhaseNoise, 74% Spectral Efficiency, GA optimized FIR impulse radio UWB transmitter, PrimeAsia 2010, pp. 384 - 387, 2010.

[146] Chengwen Liu,Rui He,Xueyi Yu,Woogeun Rhee,Zhihua Wang, A Latency-Proof Quantization Noise Reduction Method for Digitally-Controlled Ring Oscillators, MWSCAS 2010, pp. 97 – 100, 2010.

[147] Woogeun Rhee,Ni Xu,Bo Zhou,Zhihua Wang, Low Power, Non Invasive UWB Systems for WBAN and Biomedical Applications, ICTC 2010, pp. 35 - 40, 2010.

[148] Zhuo Zhang,Jun Li,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, A Digitally Reconfigurable Auto Amplitude Calibration Method for Wide Tuning Range VCO Design, ICSICT 2010, pp. 542 - 544, 2010.

[149] Bo Zhou,Rui He,Jian Qiao,Jinghui Liu,Woogeun Rhee,Zhihua Wang, A Low Data Rate FM-UWB Transmitter with Δ−Σ Based Sub-Carrier Modulation and Quasi-Continuous Frequency-Locked Loop, A-SSCC 2010, pp. 1 - 4, 2010.

[150] Rui He,Chengwen Liu,Xueyi Yu,Woogeun Rhee,Joon Young Park,Kyongsu Lee,Changhyun Kim,Zhihua Wang, A Low-Cost, Leakage-Insensitive Semi-Digital PLL with Linear Phase Detection And FIR-Embedded Digital Frequency Acquisition, A-SSCC 2010, pp. 1 - 4, 2010.

[151] Yutao Liu,Woogeun Rhee,Ziqiang Wang,Zhihua Wang, Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit, APCCAS 2010, pp. 939 - 942, 2010.

[152] Jun Li,Ni Xu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, Reconfigurable, Fast AFC Technique Using Code Estimation and Binary Search Algorithm for 0.2-6GHz Software-Defined Radio Frequency Synthesis, APCCAS 2010, pp. 1135 - 1138, 2010.

[153] Baoyong Chi,Li Zhang,Woogeun Rhee,Zhihua Wang,Hongyi Chen, A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesizer, International Journal of Electronics, Vol.96, No.10, pp. 1039 - 1056, 2009.

[154] Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, An FIR-embedded noise filtering method for ΔΣ fractional-N PLL clock generators, IEEE Journal of Solid-State Circuits, Vol.44, No.9, pp. 2426 - 2436, 2009.

[155] Li Zhang,Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Wang, D.,Zhihua Wang,Hongyi Chen, A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops, IEEE Journal of Solid-State Circuits, Vol.44, No.11, pp. 2922 - 2934, 2009.

[156] Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Hyung Ki Ahn,Byeong-Ha Park,Zhihua Wang, A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications, IEEE Journal of Solid-State Circuits, Vol.44, No.8, pp. 2193 - 2201, 2009.

[157] Xueyi Yu,Woogeun Rhee,Zhihua Wang,Jung-Bae Lee,Changhyun Kim, A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation, ISSCC 2009, pp. 398 - 399, 2009.

[158] Yuanfeng Sun,Jian Qiao,Jun Li,Rui He,Chengwen Liu,Woogeun Rhee,Sung Hun Woo,Zhihua Wang, A Low-Cost, Multi-Standard ΔΣ Fractional-N Synthesizer Design for WiMAX/WLAN Applications, ISOCC 2009, pp. 100 - 103, 2009.

[159] Jian Chen,Xueyu Yu,Li Yugen,Zhihua Wang, Customized Zero Frequency Control for Hybrid FIR Noise Filtering in ΔΣ Fractional-N PLL, ISCAS 2009, pp. 2401 - 2404, 2009.

[160] Rui He,Jun Li,Woogeun Rhee,Zhihua Wang, Transient Analysis of Nonlinear Settling Behavior in Charge-Pump Phase-Locked Loop Design, ISCAS 2009, pp. 469 - 472, 2009.

[161] Jun Li,Woogeun Rhee,Zhihua Wang, A Dual-Carrier IR-Based UWB Transmitter with Improved Spectral Efficiency, ICCCAS 2009, pp. 788 - 792, 2009.

[162] Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Sangsoo Ko,Wooseung Choo,Byeong-Ha Park,Zhihua Wang, A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order ΔΣ modulation and weighted FIR filtering, A-SSCC 2009, pp. 77 - 80, 2009.

[163] Xueyi Yu,Yuanfeng Sun,Li Zhang,Woogeun Rhee,Zhihua Wang, A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering, ISSCC 2008, pp. 346 - 347. , 2008.

[164] Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang,Hyung Ki Ahn,Byeong-Ha Park, A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications, CICC 2008, pp. 753 - 756, 2008.

[165] Li Zhang,Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang,Hongyi Chen,Wang, D., A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops, A-SSCC 2008, pp. 417 - 420, 2008.

[166] Baoyong Chi,Xueyi Yu,Woogeun Rhee,Zhihua Wang, A fractional-N PLL for digital clock generation with an FIR-embedded frequency divider, ISCAS 2007, pp. 3051 - 3054, 2007.

Patents：

[1] Yugen Li，Yunzhao Nie，Zhihua Wang. Quasi balanced frequency shift keying modulation method and quasi balanced fm transmitter: China, 202210535280.0[P].

[2] Yugen Li，Su Han，Zhihua Wang. An Asymmetric Pulse UWB Transmitter System: China, 202210384491.9[P].

[3] Yugen Li,Bowen Wang, Zhihua Wang. A baseband modulation and demodulation circuit for self synchronizing pulse uwb signals: China, 202210302388.5[P]. 2023-03-14.

[4] Woogeun Rhee, Zixiang Wan, Zhihua Wang. Universal frequency modulator and frequency modulation method and device: China, 202110262312.X[P].

[5] Woogeun Rhee, Bowen Wang, Zhihua Wang. Quasi-coherent pulse ultra-wideband receiver and signal demodulation method: China, 202110229180.0[P]. 2022-4-12.

[6] Woogeun Rhee, Haixin Song, Zhihua Wang. Relay attack defense method and system based on pulse flight time ranging: China, 201910093208.5[P]. 2021-05-28.

[7] Woogeun Rhee, Yining Zhang, Ranran Zhou, Zhihua Wang. Circuit system and control method for directly demodulating frequency modulated signal based on phase-locked loop: China, 201811150180.6[P].

[8] Woogeun Rhee, Yining Zhang, Ranran Zhou, Zhihua Wang. Circuit system based on direct demodulation frequency modulated signal of phase -locked loop: China, 201821608143.0[P]. 2019-02-26.

[9] Woogeun Rhee, Yining Zhang, Ranran Zhou, Zhihua Wang. Frequency modulation signal demodulation system for detecting narrowband interference or channel change: China, 201810368445.3[P].

[10] Yajun He, Ziqiang Wang, Woogeun Rhee, Han Liu, Chun Zhang, Zhihua Wang, Fule Li. A multi-protocol phase-locked loop: China, 201611104156.X[P]. 2018-10-19.

[11] Woogeun Rhee, Xiaoyong Li, Wen Jia, Zhihua Wang. A modulator and its delay automatic calibration circuit and a delay control module: China, 201610058072.0[P]. 2018-10-09.

[12] Zhaoyang Weng, Hanjun Jiang, Jingjing Dong, Chao Yang, Woogeun Rhee, Zhihua Wang. A Gain calibration method of high pass path DAC in a two-point modulation transmitter: China, 201510194064.4[P]. 2017-04-19.

[13] Woogeun Rhee, Xican Chen, Jong Jin Kim, Dong Wook Kim, Zhihua Wang. Receiver, method of operating the receiver, and beamforming radar system including receiver: USA, US9791561 B2[P]. 2017-10-17.

[14] Zhihua Wang, Fei Chen, Woogeun Rhee. Hearing Aid Device: China, 201310625422.3[P]. 2016-08-17.

[15] Woogeun Rhee, Fei Chen, Jong Jin Kim, Dong Wook Kim, Zhihua Wang. Apparatus and method for UWB communication: China, 201310354498.7[P]. 2017-12-01.

[16] Shuli Geng, Woogeun Rhee, Jong Jin Kim, Dong Wook Kim, Zhihua Wang. Apparatus and method for producing the Gauss pulse: China, 201310353879.3[P]. 2017-12-08.

[17] Woogeun Rhee, Fei Chen, Jong Jin Kim, Dong Wook Kim, Zhihua Wang. Apparatus and method for ultra wideband communication using dual band pass filter: USA, US9172425 B2[P]. 2015-10-27.

[18] Shuli Geng, Woogeun Rhee, Jong Jin Kim, Dong Wook Kim, Zhihua Wang. Apparatus and method for generating gaussian pulse and ultra wideband communication apparatus for generating gaussian pulse: USA, US9036679 B2[P]. 2015-05-19.

[19] Woogeun Rhee, Bo Zhou, Jong-Jin Kim, Dong-Wook Kim, Zhihua Wang. Transmitter and receiver for reducing power consumption in FM-UWB communication system: China, 201310088632.3[P]. 2017-06-09.

[20] Woogeun Rhee, Bo Zhou, Jong-Jin Kim, Dong-Wook Kim, Zhihua Wang. Transmitter and receiver for reducing power consumption in fm-uwb communication system: USA, US9253730 B2[P]. 2016-02-02.

[21] Woogeun Rhee, He Rui, Xueyi Yu, Tae-Young Oh, Joo-Sun Choi, Zhihua Wang. Phase-locked-loop circuit including digitally-controlled oscillator: USA, US8368440 B2[P]. 2013-02-05.

[22] Woogeun Rhee, Xueyi Yu, Sung Cheol Shin, Zhihua Wang. Delay locked loop using hybrid FIR filtering technique and semiconductor memory device having the same: USA, US8310886 B2[P]. 2012-11-13.

[23] Woogeun Rhee, Xueyi Yu, Joon-Young Park, Zhihua Wang. Delay locked loop and method and electronic device including the same: USA, US8295106 B2[P]. 2012-10-23.

[24] Woogeun Rhee, Xueyi Yu, Yuanfeng Sun, Sang-Soo Ko, Byeong-Ha Park, Hyung-Ki Ahn, Woo-Seung Choo, Zhihua Wang. Frequency divider, frequency synthesizer and application circuit: USA, US8446190 B2[P]. 2013-05-21.

Books：

[1] Ni Xu, Woogeun Rhee (Editor), Zhihua Wang. Chapter 17: Hybrid Phase Modulators with Enhanced Linearity. in Wireless Transceiver Circuits System Perspectives and Design Aspects. Boca Raton: CRC Press, 2015.

[2] Xueyi Yu, Woogeun Rhee, Zhihua Wang. Chapter 12: Delta-Sigma Fractional-N Phase-Locked Loop. in CMOS Nanoelectronics: Analog and RF VLSI Circuits. USA: McGraw Hill Publishers, 2011.

Papers before joining ICAS：

[1]W. Rhee, H. Ainspan, D. Friedman, T. Rasmus, S. Garvin, and C. Cranford, “A continuously tunable LC-VCO PLL with bandwidth linearization techniques for PCI Express Gen2 Applications,” Journal of Semiconductor Technology and Science, vol. 8, pp.200-209, Sept. 2008.
[2]W. Rhee, K. Jenkins, J. Liobe, and H. Ainspan, “Experimental analysis of substrate noise effect on PLL performance,” IEEE Trans. on Circuits and Systems II, vol. 55, pp. 638-642, July 2008. (SCI)
[3]W. Rhee, B. Parker, and D. Friedman, “A semidigital delay-locked loop using an analog-based finite state machine,” IEEE Transactions on Circuits and Systems II, vol. 50, pp. 635-639, Nov. 2004. (SCI)
[4]W. Rhee, “Practical design aspects in fractional-N frequency synthesis,” Analog Circuit Design, Edited by A. van Roermund, M. Steyaert, and J. Huijsing, Springer Publishers, pp. 3-26, 2003. (SCI)
[5]W. Rhee, B. Song, and A. Ali, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order delta-sigma modulator,” Phase-Locking in High Performance Systems: From Devices to Architectures, Edited by B. Razavi, John Wiley & Sons, Inc., pp. 596-602, 2003. (SCI)
[6]W. Rhee, B. Bisanti, and A. Ali, “An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 515-520, Apr. 2002. (SCI)
[7]W. Rhee, B. S. Song, and A. Ali, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order delta-sigma modulator,” IEEE Journal of Solid- State Circuits, vol. 35, pp. 1453-1460, Oct. 2000. (SCI)
[8]W. Rhee, et al., “A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5Gb/s PCI Express Gen2 application,” in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2007, pp. 63-66.
[9]W. Rhee, et al., “A 10-Gb/s CMOS clock and data recovery circuits using a secondary delay-locked loop,” in Proc. IEEE Custom Integrated Circuits Conf.(CICC), Sept. 2003, pp. 81-84.
[10]W. Rhee, B. Bisanti, and A. Ali, “An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution,” in Proc. IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2000, pp. 224-227.
[11]W. Rhee, A. Ali, and B. S. Song, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order delta-sigma modulator,” in IEEE International Solid-State Circuits Conference (ISSCC) Digest Tech. Papers, Feb. 2000, pp. 198-199.
[12]W. Rhee, “Design of low jitter 1-GHz phase-locked loops for digital clock generation,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May, 1999, pp. 520-523.
[13]W. Rhee, “Design of high performance CMOS charge pumps for phase-locked loops,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May, 1999, pp. 545-548.
[14]W. Rhee and A. Ali, “An on-chip phase compensation technique in fractional-N frequency synthesis,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May, 1999, pp. 363-366.
[15]W. Rhee, “A low power, wide linear-range CMOS voltage-controlled oscillator,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May, 1998, pp. 85-88.