题目/Title：A 2.74–5.37GHz boosted-gain type-I PLL with <15% loop filter area

作者/Author：
                        Yuanfeng Sun,Jun Li,Zhuo Zhang,Min Wang,Ni Xu,Hang Lv,Woogeun Rhee,Yongming Li,Zhihua Wang

会议/Conference：RFIC 2012

地点/Location：Montreal, QC

年份/Issue Date：2012.17-19 June

页码/pages：pp. 181 - 184

摘要/Abstract：
This paper describes a 64% locking-range type-I LC PLL architecture with a small loop filter area. By employing a dual-path LC VCO with a boosted open-loop gain at dc, a reference spur or a static phase error problem with a large frequency offset in the type-I PLL is alleviated. The prototype PLL is implemented in 0.13μm CMOS, achieving 2.74-to-5.37GHz locking range with <;-50dBc reference spur over active locking range.