题目/Title：A PVT-Insensitive Self-Dithered TDC Design by Utilizing a DS DLL

作者/Author：韩一帜,李宇根,王志华
                        Yizhi Han,Woogeun Rhee,Zhihua Wang

会议/Conference：MWSCAS 2012

地点/Location：Boise, Idaho, USA

年份/Issue Date：2012.5-8 Aug.

页码/pages：pp. 542 - 545

摘要/Abstract：
This paper describes a DS dithered time-to-digital converter (TDC) design for all-digital phase-locked loops (ADPLLs). Different from other DS modulated TDCs, the proposed TDC employs a DS delay-locked loop (DLL) to achieve both noise-shaped dithering and PVT-insensitive time resolution. Simulation results show that the proposed TDC significantly improves the fractional spur performance even with TDC nonlinearity considered. The TDC designed in 65nm CMOS occupies an area of <0.06mm2 and consumes 2.2mW.