题目/Title：A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering

作者/Author：
                        Xueyi Yu,Yuanfeng Sun,Li Zhang,Woogeun Rhee,Zhihua Wang

会议/Conference：ISSCC 2008

地点/Location：San Francisco, CA

年份/Issue Date：2008.3-7 Feb.

页码/pages：pp. 346 - 347.

摘要/Abstract：
This paper describes a noise filtering method for quantization noise reduction that is not sensitive to PVT variations. The resulting fractional-N PLL clock generator is the first one demonstrated with an oversampling ratio (OSR) of about 10.