题目/Title：A PLL/DLL Based CDR with Delta-Sigma Frequency Tracking and Low Algorithmic Jitter Generation

作者/Author：耿树理,徐妮,李俊,喻学艺,李宇根,王志华
                        Shuli Geng,Ni Xu,Jun Li,Xueyi Yu,Woogeun Rhee,Zhihua Wang

会议/Conference：ISCAS 2013

地点/Location：Beijing, China

年份/Issue Date：2013.19-23 May

页码/pages：pp. 1179 - 1182

摘要/Abstract：
A delay- and phase-locked loop (D/PLL) based clock and data recovery (CDR) system enables an independent bandwidth control for jitter transfer and jitter tolerance but requires careful loop design with PVT-sensitive analog building blocks. In this work, an all-digital DLL and a digitally-controlled type-I boosted-gain fractional-N PLL followed by an injection-locked oscillator (ILO) are designed to realize a semi-digital CDR system with enhanced frequency tracking capability and low algorithm jitter generation. The proposed CDR designed in 90nm CMOS consumes 26.4mW from a 1.2V supply and occupies the active area of 1.17mm2.