题目/Title：A fractional-N PLL for digital clock generation with an FIR-embedded frequency divider

作者/Author：
                        Baoyong Chi,Xueyi Yu,Woogeun Rhee,Zhihua Wang

会议/Conference：ISCAS 2007

地点/Location：New Orleans, LA

年份/Issue Date：2007.27-30 May

页码/pages：pp. 3051 - 3054

摘要/Abstract：
In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequential outputs of a ΔΣ modulator, finite impulse response (FIR) filtering with respect to modulator noise is realized in the PLL, resulting in quantization noise reduction in high frequencies. Hence, a low oversampling ratio (OSR) ΔΣ fractional-N PLL can be achieved without increasing quantization noise. Architecture comparison and simulation results are also presented.