题目/Title：All-digital PLL with ΔΣ DLL embedded TDC

作者/Author：
                        Y. Han,D. Lin,Shuli Geng,Ni Xu,Woogeun Rhee,T-Y Oh,Zhihua Wang

期刊/Journal：Electronics Letters

年份/Issue Date：2013Jan.

卷（期）及页码/Volume（No.）&pages：Vol.49, No.2, pp. 93 - 94

摘要/Abstract：
An all-digital PLL (ADPLL) which employs a ΔΣ delay-locked loop (DLL) to achieve a PVT-insensitive time resolution of the time-to-digital converter (TDC) as well as noise-shaped dithering is implemented in 65 nm CMOS. Experimental results show that the proposed method can achieve spur reduction with slight degradation of in-band phase noise. The 1.8 GHz ADPLL consumes 14.3 mW, while the TDC with the ΔΣ DLL consumes 2.1 mW.