个人简介

所发表的论文：

[1] Xuqiang Zheng,Fangxu Lv,Lei Zhou,Danyu Wu,Jin Wu,Chun Zhang,Woogeun Rhee,Xinyu Liu, Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators, IEEE Journal of Solid-State Circuits, Vol.55, No.6, pp. 1651 - 1664, 2020.

[2] Fangxu Lv,Jianye Wang,Xuqiang Zheng,Ziqiang Wang,Yajun He,Hao Ding,Yongcong Liu,Chun Zhang,Zhihua Wang, A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65nm CMOS Technology, Journal of Harbin Institute of Technology (New Series), Vol.26, No.3, pp. 50-57, 2019.

[3] Fangxu Lv,Xuqiang Zheng,Jianye Wang,Guoli Zhang,Ziqiang Wang,Shuai Yuan,Yajun He,Chun Zhang,Zhihua Wang, A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology, Analog Integrated Circuits and Signal Processing, Vol.99, No.1, pp. 147 - 157, 2019.

[4] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shuai Yuan,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang, A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS, IEEE Journal of Solid-State Circuits, Vol.52, No.11, pp. 2963 - 2978, 2017.

[5] Fangxu Lv,Xuqiang Zheng,Shuai Yuan,Ziqiang Wang,Yajun He,Chun Zhang,Zhihua Wang,Fangxu Lv,Jianye Wang, A 40-80Gb/s PAM4 Wireline Transmitter in 65nm CMOS Technology, MWSCAS 2017, pp. 539 - 542, 2017.

[6] Fangxu Lv,Xuqiang Zheng,Ziqiang Wang,Yajun He,Chun Zhang,Jianye Wang,Zhihua Wang,Hanjun Jiang, Design of 80-Gb/s PAM4 Wireline Receiver in 65-nm CMOS Technology, EDSSC 2017, pp. 1 - 2, 2017.

[7] Fangxu Lv,Jianye Wang,Xuqiang Zheng,Shuai Yuan,Ziqiang Wang,Yajun He,Zhihua Wang,Hanjun Jiang, A 10–60 Gb/s wireline transmitter with a 4-tap multiple-MUX based FFE, EDSSC 2017, pp. 1 - 2, 2017.

[8] Xuqiang Zheng,Fangxu Lv,Feng Zhao,Shigang Yue,Chun Zhang,Ziqiang Wang,Fule Li,Hanjun Jiang,Zhihua Wang, A 10 GHz 56 fsrms-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS, CICC 2017, pp. 1 - 4, 2017.

[9] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shigang Yue,Ziqiang Wang,Fule Li,Hanjun Jiang,Zhihua Wang, A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS, CICC 2017, pp. 1 - 4, 2017.

[10] Xuqiang Zheng,Fule Li,Zhijun Wang,Weitao Li,Wen Jia,Zhihua Wang,Shigang Yue, An S/H circuit with parasitics optimized for IF-sampling, Journal of Semiconductors, Vol.37, No.6, pp. 065005-1 - 5, 2016.

[11] Xuqiang Zheng,Zhijun Wang,Fule Li,Feng Zhao,Shigang Yue,Chun Zhang,Zhihua Wang, A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.63, No.9, pp. 1381 - 1392, 2016.

[12] Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.63, No.7, pp. 939 - 949, 2016.

[13] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang, A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS , ESSCIRC 2016, pp. 305 - 308, 2016.

[14] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 80mW 40Gb/s Transmitter with Automatic Serializing Time Window Search and 2-tap Pre-emphasis in 65nm CMOS Technology, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.62, No.5, pp. 1441 - 1450, 2015.

[15] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Wen Jia,Liji Wu,Chun Zhang,Zhihua Wang, 10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed-signal adaption in 65 nm CMOS technology, Electronics Letters, Vol.51, No.21, pp. 1645 - 1647, 2015.

[16] Weidong Cao,Ziqiang Wang,Dongmei Li,Xuqiang Zheng,Ke Huang,Shuai Yuan,Fule Li,Zhihua Wang, A 40Gb/s 27mW 3-tap Closed-loop Decision Feedback Equalizer in 65nm CMOS, NEWCAS 2015, pp. 1 - 4, 2015.

[17] Weidong Cao,Ziqiang Wang,Dongmei Li,Xuqiang Zheng,Fule Li,Chun Zhang,Zhihua Wang, A 40Gb/s 39mW 3-tap Adaptive Closed-loop Feedback Equalizer in 65nm CMOS, MWSCAS 2015, pp. 1 - 4, 2015.

[18] Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Peng Wang,Wen Jia,Chun Zhang,Zhihua Wang, A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS, ESSCIRC 2015, pp. 144 - 147, 2015.

[19] Weidong Cao,Xuqiang Zheng,Ziqiang Wang,Dongmei Li,Fule Li,Shigang Yue,Zhihua Wang, A 15Gb/s Wireline Repeater in 65nm CMOS Technology, EDSSC 2015, pp. 590 - 593, 2015.

[20] Ke Huang,Deng Luo,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 190mW 40Gbps SerDes Transmitter and Receiver Chipset in 65nm CMOS Technology, CICC 2015, pp. 1 - 4, 2015.

[21] Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Wen Jia,Chun Zhang,Zhihua Wang, A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS[C], CICC 2015, pp. 1 - 4, 2015.

[22] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Ni Xu,Woogeun Rhee,Liji Wu,Chun Zhang, A 4.8-mW/Gb/s 9.6-Gb/s 5+1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.61, No.4, pp. 209 - 213, 2014.

[23] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, 2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology, Electronics Letters, Vol.50, No.25, pp. 1910 - 1912, 2014.

[24] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, 2 GHz sub-harmonically injectin-locked PLL with mixer-based injection timing control in 0.18 μm CMOS technology, Electronics Letters, Vol.50, No.12, pp. 855 - 857, 2014.

[25] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang, A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-mu m CMOS technology, Analog Integrated Circuits and Signal Processing, Vol.81, No.3, pp. 777 - 788, 2014.

[26] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Kunzhi Yu,Chun Zhang,Zhihua Wang, A 5+ 1-lane 3-10 Gbps 3.5 mW/Gb/s source synchronous receiver in 65 nm CMOS technology, Analog Integrated Circuits and Signal Processing, Vol.80, No.3, pp. 519 - 529, 2014.

[27] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang, A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology, Analog Integrated Circuits & Signal Processing, Vol.81, No.3, pp.777 - 788, 2014.

[28] Linghan Wu,Shuai Yuan,Xuqiang Zheng,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 10Gb/s source-synchronous transmitter in 65nm CMOS technology, EDSSC 2014, pp. 1 - 2, 2014.

[29] Peng Wang,Xuqiang Zheng,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS, EDSSC 2014, pp. 1 - 2, 2014.

[30] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang, A 10Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65nm CMOS technology, EDSSC 2014, pp. 1 - 2, 2014.

[31] Linghan Wu,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Chun Zhang,Zhihua Wang, Co-design of 40Gb/s equalizers for wireline transceiver in 65nm CMOS technology, EDSSC 2014, pp. 1 - 2, 2014.

[32] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 75mW 50Gbps SerDes Transmitter with Automatic Serializing Time Window Search in 65nm CMOS technology, CICC 2014, pp. 1 - 4, 2014.

[33] Kunzhi Yu,Xuqiang Zheng,Ke Huang,Ma Xuan,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS, VLSI-DAT 2013, pp. 1 - 4, 2013.

[34] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Liji Wu,Zhihua Wang, A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology, ASICON 2013, pp. 1 – 4, 2013.

[35] Linghan Wu,Ziqiang Wang,Ke Huang,Shuai Yuan,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 10Gb/s analog equalizer in 0.18um CMOS, ASICON 2013, pp. 1 - 4, 2013.

[36] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS, MWSCAS 2012, pp. 932 - 935, 2012.

[37] Kunzhi Yu,Ziqiang Wang,Xuan Ma,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS, MWSCAS 2012, pp. 936 - 939, 2012.

[38] Shijie Hu,Chen Jia,Ke Huang,Chun Zhang,Xuqiang Zheng,Zhihua Wang, A 10Gbps CDR based on Phase Interpolator for Source Synchronous Receiver in 65nm CMOS, ISCAS 2012, pp. 309 - 312, 2012.

[39] Ke Huang,Chen Jia,Xuqiang Zheng,Ni Xu,Chun Zhang,Woogeun Rhee,Zhihua Wang, A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology, ISCAS 2012, pp. 313 - 316, 2012.

[40] Shuai Yuan,Liji Wu,Ziqiang Wang,Xiangmin Zhang,Xuqiang Zheng, Research on high speed mixed-signal SoC verification based on NanoSim-VCS with a 4.8 Gb/s SerDes transmitter, ICSICT 2012, 2012.

[41] Ying Cheng,Fule Li,Xuqiang Zheng,Chun Zhang, Self-Calibrating On-Chip Termination Resistor for High-Speed SerDes, CECNet 2011, pp. 5207 - 5210, 2011.

所持专利：

[1] 曹卫东, 王自强, 郑旭强, 黄柯, 李福乐. 一种高速电路的带上拉PMOS管的动态锁存器: 中国, 201510497993.2[P]. 2017-12-29.

[2] 黄柯, 王自强, 郑旭强, 张春, 王志华. 一种新型的高速串行接口发射机: 中国, 201410641518.3[P]. 2017-07-07.

[3] 黄柯, 王自强, 郑旭强, 张春, 王志华. 一种新型的高速串行接口发射机: 中国, 201410475671.3[P]. 2016-03-30.

[4] 郑旭强, 黄柯, 李福乐, 王自强, 张春, 王志华. 源同步高速串行接口的时钟通路前端放大电路: 中国, 201310629540.1[P]. 2016-08-17.

[5] 袁帅, 王自强, 郑旭强, 乌力吉, 张春, 王志华. 用于高速串行接口接收端的1/4速率4抽头判决反馈均衡器: 中国, 201310483312.8[P]. 2016-05-18.

[6] 徐冠南, 贾晨, 王自强, 郑旭强, 张春, 姜汉钧, 陈虹, 王志华. 一种采用数字滑模变结构控制的Buck型开关电源转换器: 中国, 201210500397.1[P]. 2014-12-10.

[7] 胡世杰, 王自强, 黄柯, 郑旭强, 李福乐, 马轩, 俞坤治, 张春, 王志华. 高速时钟数据恢复电路中的时钟相位判断电路和判断方法: 中国, 201210478209.X[P]. 2015-10-14.

加入ICAS之前的论文：

[1]周继承，郑旭强,刘福. SiC薄膜材料与器件最新研究进展. 材料导报，2006，10 
[2]Zhou Jicheng(周继承)，Zheng xueqiang(郑旭强). Structure and electronical properties of SiC films deposited by RF magnetron sputtering，Transactions of Nonferrous Metals Society of China, 2006，11(SCI检索)
[3]周继承,郑旭强．磁控溅射碳化硅薄膜及其光电特性研究． 功能材料，2006，10 （EI检索）
[4]周继承,郑旭强．磁控溅射制备SiC薄膜及其电学特性研究，真空科学与技术学报，2006，11（EI检索）