题目/Title：A 10Gbps CDR based on Phase Interpolator for Source Synchronous Receiver in 65nm CMOS

作者/Author：胡世杰,贾晨,黄柯,张春,郑旭强,王志华
                        Shijie Hu,Chen Jia,Ke Huang,Chun Zhang,Xuqiang Zheng,Zhihua Wang

会议/Conference：ISCAS 2012

地点/Location：Seoul, Korea

年份/Issue Date：2012.20-23 May

页码/pages：pp. 309 - 312

摘要/Abstract：
In this paper, a 10Gbps PI-based CDR circuit is presented in 65nm CMOS technology. The circuit is composed of a phase selector, a phase interpolator, a sample unit, a synchronize unit, a phase detector, and CDR logic. Half-rate clock is adopted to lessen the problems caused by speed clocks and reduce power. The simulated worst phase step of phase interpolator is 26.7% higher to the average phase error. The power consumption is 15mW for 1V supply.