题目/Title:A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology
作者/Author:
Ke Huang,Chen Jia,Xuqiang Zheng,Ni Xu,Chun Zhang,Woogeun Rhee,Zhihua Wang
会议/Conference:ISCAS 2012
地点/Location:Seoul, Korea
年份/Issue Date:2012.20-23 May
页码/pages:pp. 313 - 316
摘要/Abstract:
This paper describes the design of a low-jitter source-synchronous link transmitter macro for data rates of 9.6 Gb/s. The transmitter macro consists of 5 data channels plus 1 forwarded-clock channel. A low jitter PLL with bandwidth linearization is employed to achieve 0.66ps rms jitter. The power supply induced jitter is minimized by employing a hybrid clock distribution network which is proposed for both jitter and power consideration. To minimize the influence of PVT variation, Successive Approximation Register (SAR) sub block is implemented to accurately set the on chip impedance and the signal amplitude. A CML driver with 4 tap feed forward equalizer is implemented to compensate the channel loss. The transmitter is implemented in 65nm CMOS technology, the active chip area is 3.12 mm2.