题目/Title：A 40Gb/s 39mW 3-tap Adaptive Closed-loop Feedback Equalizer in 65nm CMOS

作者/Author：
                        Weidong Cao,Ziqiang Wang,Dongmei Li,Xuqiang Zheng,Fule Li,Chun Zhang,Zhihua Wang

会议/Conference：MWSCAS 2015

地点/Location：Fort Collins, Colorado USA

年份/Issue Date：2015.2-5 Aug.

页码/pages：pp. 1 - 4

摘要/Abstract：
This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate adaptively at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap differential pairs within the clock-control summers array (CCSA) to accomplish the 2nd and 3rd tap stages design. Last, the sign-sign least-mean square (SSLMS) algorithm is adopted in the DFE to adjust the tap weight automatically. The total power consumption of the 3-tap DFE core is 39mW under 1V supply, achieving 1 pJ/bit energy efficiency