题目/Title：A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS

作者/Author：
                        Kunzhi Yu,Ziqiang Wang,Xuan Ma,Xuqiang Zheng,Chun Zhang,Zhihua Wang

会议/Conference：MWSCAS 2012

地点/Location：Boise, Idaho, USA

年份/Issue Date：2012.5-8 Aug.

页码/pages：pp. 936 - 939

摘要/Abstract：
This paper describes a 6.4Gb/s data lane circuit in 65nm CMOS process. The data lane circuit consists of an offset cancellation continuous time linear equalizer and a half-rate digital CDR; the CDR bandwidth is programmable by using a digital FIR filter. A common-mode level shift function is implemented in order to use NMOS input CML circuit. The design can compensate over 8 dB channel loss with offset-calibrated and low noise. The area for one data lane is 0.045 μm2 and power consumption is 24.5mW for 1.2V supply.