题目/Title：A 10 GHz 56 fsrms-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS

作者/Author：
                        Xuqiang Zheng,Fangxu Lv,Feng Zhao,Shigang Yue,Chun Zhang,Ziqiang Wang,Fule Li,Hanjun Jiang,Zhihua Wang

会议/Conference：CICC 2017

地点/Location：Austin, TX, USA

年份/Issue Date：2017.30 April-3 May

页码/pages：pp. 1 - 4

摘要/Abstract：
This paper presents a low jitter ring-VCO based injection-locked clock multiplier (RILCM) with a phase-shift detection based hybrid frequency tracking loop (FTL). A fullswing pseudo-differential delay cell (FS-PDDC) is proposed to lower the device noise to phase noise conversion. To obtain high operation speed, high detection accuracy, and low output disturbance, a compact timing-adjusted phase detector (TPD) tightly combining with a well-matched charge pump (CP) is designed. Additionally, a lock-loss detection and lock recovery (LLD-LR) scheme is devised to equip the RILCM with a similar lock-acquisition ability to conventional PLL, thus excluding the initial frequency setup aid and preventing potential lock loss. Implemented in 65 nm CMOS, the RILCM occupies an active area of 0.07 mm2 and consumes 59.4 mW at 10 GHz. The measured results show that it achieves 56.1 fs rms-jitter and - 57.13 dBc spur level. The calculated figure-of-merit (FOM) is -247.3 dB, which is better than previous RILCMs and even comparable to those large-area LC-ILCMs.