题目/Title：A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS

作者/Author：
                        Kunzhi Yu,Xuqiang Zheng,Ke Huang,Ma Xuan,Ziqiang Wang,Chun Zhang,Zhihua Wang

会议/Conference：VLSI-DAT 2013

地点/Location：Hsinchu

年份/Issue Date：2013.22-24 April

页码/pages：pp. 1 - 4

摘要/Abstract：
This paper presents a source synchronous receiver data lane design in 65nm CMOS process. The data lane circuit consists of a pre-amplifier which can compensate over 8dB channel loss and a half-rate digital CDR based on phase-interpolator. The CDR bandwidth is programmable by using a digital FIR filter. This design uses variable offset amplifier technology to increase sensitivity of the receiver. And a common-mode level shift function is implemented in order to increase the bandwidth of the pre-amplifier. The area for one data channel without ESD and PAD is 0.05 mm^2 and power consumption is 35mw for 1.2V supply.