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Ke Huang

Biography

Enrollment Date: 2009

Graduation Date：2015

Degree：Ph.D.

Defense Date：2015.06.07

Advisors：Zhihua Wang Chun Zhang Ziqiang Wang

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Study on Key Techniques of High Performance and Low Power HighSpeedSerial Link

Abstract:
Higherdata rate and lower power consumption are important trends in the development of high speed serial link. As the link data rate keeps rising, high speed serial link suffers from design challenges caused by limited bandwidth, stringent timing, heavy channel loss and high power consumption. In this dissertation, the principle and commonly used techniquesof high speed serial link are introduced and summarized.Focusing on channel equalization, clock generation and recovery, low power and high data rate design, this dissertationhas the following achievements: Firstly, based on the Intel QPI protocol, a 10Gb/s receiver with 5 data lanes and 1 clock lane is realized with SMIC 65nm technology. The receiver employs a number of design techniques to improve the link performance, including the clock lane optimization, ring counter based CDR logic and so on. As a result,the receiver is able to run at 10Gb/s with a BER less than 10-12 and the power efficiency is 3.5mW/Gb/s. Secondly, a voltage mode transmitter with a current mode low frequency equalizer is proposed. The transmitter combining aconventional feed forward equalizer and alow frequency equalizer is able to equalize the low frequency loss contributed by skin effect. The transmitter is fabricated in TSMC 65nm technology, which is able to work at 20Gb/s. Experiment shows that the total jitter of 20Gb/s data eye is 19ps for 10-12 BERand the power consumption is only 39mW. The transmitter output data passesthrough a FR4 channeland the low frequency equalization effect is verified underdata rates from 8Gb/s to 10Gb/s. Furthermore, a series of design techniques are put forwardto optimize 40Gb/s serial link design. In order to guarantee transmitter timing, a serializing time window search loop is proposed,which greatly reduces power consumption at the same time. In addition, a simple realization of transmitter feed forward equalizer based on open loop delay is adoptedto save equalizer power and area.Thistransmitter employs a sub-harmonically injection locked PLL to generate low jitter clock, and a mixer based injection timing control method is proposed to control injection timing.Moreover, the receiver comprisespower efficient front end circuits including current-integrating feed forward equalizers and cascaded dynamiclatches for sampling. Fabricated in TSMC 65nm technology, the transceiver is able to operatefrom 38.4Gb/sto 46.4Gb/s with aBER less than 10-12 and the transmitter alone can work up to 54Gb/s. When operatingat 40Gb/s, the total power consumption of the transceiver is only 190mW. The total jitter of 40Gb/s transmitterdata eye is 6.7ps for 10-12BER and the receiver is able to equalize 11dB channel loss.

Publications

Papers：：

[1] Naiwen Zhou,Ke Huang,Fangxu Lv,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 76 mW 40-Gb/s SerDes Transmitter With 64:1 MUX In 65-nm CMOS Technology, ICEIEC 2016, pp. 155 - 158, 2016.

[2] Naiwen Zhou,Ertai Duo,Ziqiang Wang,Hanjun Jiang,Ke Huang, A 3-Tap Feed-Forward-Equalizer in 65nm CMOS , Microelectronics, pp. 764 - 768 , 2015.

[3] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 80mW 40Gb/s Transmitter with Automatic Serializing Time Window Search and 2-tap Pre-emphasis in 65nm CMOS Technology, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.62, No.5, pp. 1441 - 1450, 2015.

[4] Weidong Cao,Ziqiang Wang,Dongmei Li,Xuqiang Zheng,Ke Huang,Shuai Yuan,Fule Li,Zhihua Wang, A 40Gb/s 27mW 3-tap Closed-loop Decision Feedback Equalizer in 65nm CMOS, NEWCAS 2015, pp. 1 - 4, 2015.

[5] Ke Huang,Deng Luo,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 190mW 40Gbps SerDes Transmitter and Receiver Chipset in 65nm CMOS Technology, CICC 2015, pp. 1 - 4, 2015.

[6] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Ni Xu,Woogeun Rhee,Liji Wu,Chun Zhang, A 4.8-mW/Gb/s 9.6-Gb/s 5+1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.61, No.4, pp. 209 - 213, 2014.

[7] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, 2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology, Electronics Letters, Vol.50, No.25, pp. 1910 - 1912, 2014.

[8] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, 2 GHz sub-harmonically injectin-locked PLL with mixer-based injection timing control in 0.18 μm CMOS technology, Electronics Letters, Vol.50, No.12, pp. 855 - 857, 2014.

[9] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Kunzhi Yu,Chun Zhang,Zhihua Wang, A 5+ 1-lane 3-10 Gbps 3.5 mW/Gb/s source synchronous receiver in 65 nm CMOS technology, Analog Integrated Circuits and Signal Processing, Vol.80, No.3, pp. 519 - 529, 2014.

[10] Chenlong Hou,Ziqiang Wang,Ke Huang,Chun Zhang,Zhihua Wang, A 20 GHz PLL for 40 Gbps SerDes application with 4 bit switch-capacitor adaptive controller, EDSSC 2014, pp. 1 - 2, 2014.

[11] Linghan Wu,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Chun Zhang,Zhihua Wang, Co-design of 40Gb/s equalizers for wireline transceiver in 65nm CMOS technology, EDSSC 2014, pp. 1 - 2, 2014.

[12] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 75mW 50Gbps SerDes Transmitter with Automatic Serializing Time Window Search in 65nm CMOS technology, CICC 2014, pp. 1 - 4, 2014.

[13] Kunzhi Yu,Xuqiang Zheng,Ke Huang,Ma Xuan,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS, VLSI-DAT 2013, pp. 1 - 4, 2013.

[14] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Liji Wu,Zhihua Wang, A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology, ASICON 2013, pp. 1 – 4, 2013.

[15] Linghan Wu,Ziqiang Wang,Ke Huang,Shuai Yuan,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 10Gb/s analog equalizer in 0.18um CMOS, ASICON 2013, pp. 1 - 4, 2013.

[16] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS, MWSCAS 2012, pp. 932 - 935, 2012.

[17] Shijie Hu,Chen Jia,Ke Huang,Chun Zhang,Xuqiang Zheng,Zhihua Wang, A 10Gbps CDR based on Phase Interpolator for Source Synchronous Receiver in 65nm CMOS, ISCAS 2012, pp. 309 - 312, 2012.

[18] Ke Huang,Chen Jia,Xuqiang Zheng,Ni Xu,Chun Zhang,Woogeun Rhee,Zhihua Wang, A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology, ISCAS 2012, pp. 313 - 316, 2012.