题目/Title：Co-design of 40Gb/s equalizers for wireline transceiver in 65nm CMOS technology

作者/Author：
                        Linghan Wu,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Chun Zhang,Zhihua Wang

会议/Conference：EDSSC 2014

地点/Location：Chengdu, China

年份/Issue Date：2014.18-20 Jun.

页码/pages：pp. 1 - 2

摘要/Abstract：
This paper describes the co-design of equalizers for 40Gb/s transceiver. A feed forward equalizer (FFE) is applied to the transmitter, while an adaptive continuous time linear equalizer (CTLE) is applied to the receiver. The innovation is that both equalizers cooperate with each other to equalize the channel, and T-coil networks are used with ESD protection circuits in both transmitter's output and receiver's input to realize impendence matching and bandwidth enhancement. The simulation shows that, the output peak-to-peak jitter is 6.3ps when the transceiver delivers 40Gb/s PRBS7 data over a channel which has a loss of 22.8dB at 20GHz. Furthermore, the return loss at the input and the output are both less than -16dB up to 20GHz. The power consumption of this circuit is 97 mW for 1V supply.