题目/Title：A 190mW 40Gbps SerDes Transmitter and Receiver Chipset in 65nm CMOS Technology

作者/Author：黄柯,罗登,王自强,郑旭强,张春,王志华
                        Ke Huang,Deng Luo,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang

会议/Conference：CICC 2015

地点/Location：San Jose, CA, USA

年份/Issue Date：2015.28-30 Sept.

页码/pages：pp. 1 - 4

摘要/Abstract：
This paper presents a 40Gbps SerDes transceiver consuming only 190mW power. The transmitter employs serializing time window search technique and 2-tap pre-emphasis. The receiver implements power-efficient front-end circuits including current-integrating FFE and cascaded dynamic comparators. The CDR employs a bangbang phase detector, and the integral path and proportional path are separated. Fabricated in 65nm technology, the receiver BER is below 10-12 under 15dB channel loss. The total jitter of transmitter 40Gbps eye diagram is 6.7ps for 1e-12 BER. The phase noise of recovered clock is -122dBc/Hz at 1MHz and recovered data peak-peak jitter is 26ps.