Location：Home > Students > Past students
Shuai Yuan

Biography

Enrollment Date: 2011

Graduation Date：2016

Degree：Ph.D.

Defense Date：2016.05.28

Advisors：Liji Wu

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Research on Key Techniques and Design Implementation of High Speed SerDes with Intensive Equalization and Low Power Consumption

Abstract:
High speed SerDes has been widely used in many applications, such as communication networks, computer and embedded systems, along with various consumer electronics. Key techniques of high speed SerDes are deeply researched in this dissertation, mainly focusing on high data rate, low power consumption and intensive equalization. This dissertation has the following achievements at the data rates of 10 Gb/s, 25 Gb/s and 50 Gb/s, respectively. Firstly, three kinds of high speed SerDes chips are implemented at the data rate of 10 Gb/s. The first one is a 5-channel 9.6 Gb/s source-synchronous SerDes transmitter fabricated in a 65 nm CMOS technology. This transmitter includes a low jitter PLL, a low power clock distribution network and a 4-tap FFE. The power efficiency of this transmitter is 4.8 mW/Gb/s with the total jitter less than 0.2 UI. The second one is a SerDes receiver chip, which is also fabricated in a 65 nm CMOS technology. In the design of this receiver, a novel mixed-signal implementation of the DFE adaption is proposed. The power efficiency of the receiver is 5.7 mW/Gb/s when it compensates for 24.85 dB channel loss, the BER of which is less than 1e-12. The third chip is a quarter-rate 4-tap DFE using the soft-decision technique, which is proposed in this dissertation to achieve more effective equalization with less penalty of power consumption. The DFE chip is realized in a 0.18 μm CMOS technology, which can compensate for 16.3 dB channel loss when the total current is only 7.2 mA. Based on the research of 10 Gb/s SerDes, this dissertation puts forward many innovative techniques to realize a 25 Gb/s high speed SerDes transceiver with low power consumption and intensive equalization. A novel quarter-rate transmitter architecture with divider-less clock generation is proposed in the dissertation, which can significantly reduce the power of both the data lane and the clock lane. A source-series terminated driver with a 2-tap FFE and a crosstalk canceller is implemented in the transmitter chip to compensate for the channel loss and the far-end crosstalk at the same time. The receiver chip employs a power-efficient DFE using the combination of the soft-decision technique and a new dynamic structure. A hybrid alternate clock scheme is proposed to satisfy the timing requirement and reduce the power further. In addition, the DFE adaption and the baud-rate CDR based on the same dynamic structure share a set of error samplers to save both power and area markedly compared with the conventional designs. On account of these innovative techniques, a 25 Gb/s high speed SerDes transceiver is designed and fabricated in a 65 nm CMOS technology，of which the transmitter integrates four data lanes so as to lay a solid foundation for the application of 100 G Ethernet. The total power efficiency of the transmitter and receiver is less than 3 mW/Gb/s with more than 40 dB of equalization. The BER is less than 1e-12. At last, the equalization techniques for the ultra high data rate is researched in this dissertation. As a result, an ultra high speed repeater chip is fabricated in a 0.13 μm SiGe BiCMOS technology. The simulation results show that the repeater can work up to 50 Gb/s and compensate for more than 50 dB channel loss, the current consumption of which is 205 mA.

Publications

Papers：：

[1] Hong Chen,Dengjie Wang,Ziqiang Wang,Shuai Yuan,Chun Zhang,Zhihua Wang, An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS, IEEE Access, Vol.9, pp.70856-70867, 2021.

[2] Fangxu Lv,Xuqiang Zheng,Jianye Wang,Guoli Zhang,Ziqiang Wang,Shuai Yuan,Yajun He,Chun Zhang,Zhihua Wang, A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology, Analog Integrated Circuits and Signal Processing, Vol.99, No.1, pp. 147 - 157, 2019.

[3] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shuai Yuan,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang, A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS, IEEE Journal of Solid-State Circuits, Vol.52, No.11, pp. 2963 - 2978, 2017.

[4] Shuai Yuan,Liji Wu,Ziqiang Wang,Chun Zhang,Zhihua Wang,Hanjun Jiang, A 25Gb/s Serial-Link Repeater With Receiver Equalization and Transmitter De-emphasis in 0.13μm SiGe BiCMOS, MWSCAS 2017, pp. 527 - 530, 2017.

[5] Yajun He,Ziqiang Wang,Han Liu,Fangxu Lv,Shuai Yuan,Chun Zhang,Zhihua Wang,Hanjun Jiang, An 8.5–12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes, MWSCAS 2017, pp. 791 - 794, 2017.

[6] Fangxu Lv,Xuqiang Zheng,Shuai Yuan,Ziqiang Wang,Yajun He,Chun Zhang,Zhihua Wang,Fangxu Lv,Jianye Wang, A 40-80Gb/s PAM4 Wireline Transmitter in 65nm CMOS Technology, MWSCAS 2017, pp. 539 - 542, 2017.

[7] Mao Li,Yuxing Zhou,Dengjie Wang,Shuai Yuan,Wenhuan Luan,Xin Lin,Ziqiang Wang,Chun Zhang,Xiang Xie, A max mode control LDO with a good behavior at PSRR and line regulation and load regulation, EDSSC 2017, pp. 1 - 2, 2017.

[8] Wenhuan Luan,Ziqiang Wang,Shuai Yuan,Chun Zhang,Zhihua Wang, A 13.3W 5-Gb/s two-dimensional eye-opening monitor in 40nm CMOS technology, EDSSC 2017, pp. 1 - 2, 2017.

[9] Shuai Yuan,Ziqiang Wang,Yajun He,Fangxu Lv,Chun Zhang,Zhihua Wang,Hanjun Jiang, A 1.25–12.5Gb/s 5.28mW/Gb/s multi-standard serial-link transceiver with 32dB of equalization in 40nm CMOS, EDSSC 2017, pp. 1 - 2, 2017.

[10] Yajun He,Ziqiang Wang,Han Liu,Fangxu Lv,Shuai Yuan,Chun Zhang,Xiang Xie,Hanjun Jiang, An 8.5-12.5GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes, EDSSC 2017, pp. 1 - 2, 2017.

[11] Fangxu Lv,Jianye Wang,Xuqiang Zheng,Shuai Yuan,Ziqiang Wang,Yajun He,Zhihua Wang,Hanjun Jiang, A 10–60 Gb/s wireline transmitter with a 4-tap multiple-MUX based FFE, EDSSC 2017, pp. 1 - 2, 2017.

[12] Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.63, No.7, pp. 939 - 949, 2016.

[13] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Wen Jia,Liji Wu,Chun Zhang,Zhihua Wang, 10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed-signal adaption in 65 nm CMOS technology, Electronics Letters, Vol.51, No.21, pp. 1645 - 1647, 2015.

[14] Weidong Cao,Ziqiang Wang,Dongmei Li,Xuqiang Zheng,Ke Huang,Shuai Yuan,Fule Li,Zhihua Wang, A 40Gb/s 27mW 3-tap Closed-loop Decision Feedback Equalizer in 65nm CMOS, NEWCAS 2015, pp. 1 - 4, 2015.

[15] Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Peng Wang,Wen Jia,Chun Zhang,Zhihua Wang, A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS, ESSCIRC 2015, pp. 144 - 147, 2015.

[16] Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Wen Jia,Chun Zhang,Zhihua Wang, A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS[C], CICC 2015, pp. 1 - 4, 2015.

[17] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Ni Xu,Woogeun Rhee,Liji Wu,Chun Zhang, A 4.8-mW/Gb/s 9.6-Gb/s 5+1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.61, No.4, pp. 209 - 213, 2014.

[18] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang, A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-mu m CMOS technology, Analog Integrated Circuits and Signal Processing, Vol.81, No.3, pp. 777 - 788, 2014.

[19] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang, A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology, Analog Integrated Circuits & Signal Processing, Vol.81, No.3, pp.777 - 788, 2014.

[20] Linghan Wu,Shuai Yuan,Xuqiang Zheng,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 10Gb/s source-synchronous transmitter in 65nm CMOS technology, EDSSC 2014, pp. 1 - 2, 2014.

[21] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang, A 10Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65nm CMOS technology, EDSSC 2014, pp. 1 - 2, 2014.

[22] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Liji Wu,Zhihua Wang, A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology, ASICON 2013, pp. 1 – 4, 2013.

[23] Linghan Wu,Ziqiang Wang,Ke Huang,Shuai Yuan,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 10Gb/s analog equalizer in 0.18um CMOS, ASICON 2013, pp. 1 - 4, 2013.

[24] Shuai Yuan,Liji Wu,Ziqiang Wang,Xiangmin Zhang,Xuqiang Zheng, Research on high speed mixed-signal SoC verification based on NanoSim-VCS with a 4.8 Gb/s SerDes transmitter, ICSICT 2012, 2012.