Title：A 1/4 rate 4-tap decision feedback equalizer for high-speed serial interface receiving terminal
Country：China
Patent No.：201310483312.8
Legal Status：Authorized
Inventor：Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Liji Wu, Chun Zhang, Zhihua Wang
Assignee：Tsinghua University
Address：Mailbox No. 82, Beijing 100084
Filing Date：2013-10-16
Issue Date：2016-05-18
Abstract：
A high-speed serial interface receiving end of a 1/4 the rate of 4-tap decision feedback equalizer structure includes the same four channels, each channel by a sample and hold module, an adder and two latches composition first sample and hold module by using one pair of phase shift of 1/4 rate of the clock signal 90 high speed serial data input current is sampled to obtain a 1/4 rate data; judgment of the previous cycle of 1/4 The data rate of data obtained by different delays of two cascaded latches; combination of four data path delay can achieve four taps and feedback to the feedback signal of the adder in each of the front path; current adder 1/4 and 4 data rate feedback signal are summed to give a judgment of the current is 1/4 the data rate, thereby realizing the decision feedback; present invention uses 1/4 rate clock for sampling both the decision feedback taps 4 equalizer, which can meet the requirements of low power consumption and strong balance ability.
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