Title：Clock data recovery lock detection circuit adapted to variable bandwidth in high-speed serial communication

Country：China

Patent No.：201810592414.6

Legal Status：Authorized

Inventor：Shuai Yuan, Wenhuan Luan, Ziqiang Wang, Chun Zhang, Zhihua Wang

Assignee：Tsinghua University

Address：Tsinghua University,Haidian District Beijing 100084, China

Filing Date：2018-06-11

Issue Date：2021-05-04

The invention belongs to the technical field of integrated circuit design, and is a clock data recovery lock detection circuit adapted to variable bandwidth in high-speed serial communication, whereinthe lead/lag signals outputted by the filter are respectively input to two sets of shift registers and serve as mutual reset signals, and the CDR_LOCK signal is obtained by performing NOR-logic on the outputs of the two sets of shift registers. For filters of different bandwidths, the CDR lock detection circuit provided by the invention automatically adjusts the resolution of the shift registersin the lock detection circuit, which may prevent the situation that the CDR_LOCK signal cannot be stable at a high level caused by that CDR has been locked and the number of alternating occurrences ofearly and late exceeds the threshold set by the CDR lock detection circuit when the number of shift registers in the CDR lock detection circuit is small, and also may solve the problem that high level is always output regardless of whether the CDR is locked or not when the number of shift registers is large, so that the accuracy of the CDR lock detection circuit is improved, and the PCS end may also obtain the correct CDR_LOCK indication signal. 

Patent Certificate： PDF/Jpg