题目/Title：An 8.5–12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes

作者/Author：贺娅君,王自强,刘晗,吕方旭,袁帅,张春,王志华,姜汉均
                        Yajun He,Ziqiang Wang,Han Liu,Fangxu Lv,Shuai Yuan,Chun Zhang,Zhihua Wang,Hanjun Jiang

会议/Conference：MWSCAS 2017

地点/Location：Boston, MA, USA

年份/Issue Date：2017.6-9 Aug.

页码/pages：pp. 791 - 794

摘要/Abstract：
This paper presents a wideband LC PLL designed for multi-protocol serial link applications. Dual LC voltage controlled oscillator (VCO) cores are used to cover a wide frequency range while keeping a high Q factor of the LC tank, and multi-ratio dividers are used to satisfy the multi-protocol requirements. Each LC VCO adopts a 4-bit switch capacitor to increase the frequency tuning range and decrease the VCO gain. Meanwhile, the phase frequency detector (PFD), charge pump, and loop filter (LPF) are fully differential to suppress the ground and substrate noise. The PLL is implemented in SMIC 40nm CMOS technology and covers an area of 0.32mm2. The two VCOs’ free running phase noise at 1MHz are -108.1dBc/Hz and -105.7dBc/Hz respectively. The whole power of the PLL under 1.1V supply is 19.52mW, comprising 4.56mW of the VCO and 14.96mW of the other parts.