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Xinwang Zhang

Biography

Enrollment Date: 2011

Graduation Date：2015

Degree：Ph.D.

Defense Date：2015.06.06

Advisors：Baoyong Chi

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Research on Key Techniques of Software-Defined Radio Receiver Chip for Industry Specialized Applications

Abstract:

Publications

Papers：：

[1] Yang Xu,Xinwang Zhang,Zhihua Wang,Baoyong Chi, A Flexible Continuous-Time ΔΣ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.25, No.3, pp. 872 - 880, 2017.

[2] Xinwang Zhang,Bingqiao Liu,Zhihua Wang,Baoyong Chi, An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS, Microelectronics Journal, Vol.46, No.1, pp. 81 - 95, 2015.

[3] Yun Yin,Baoyong Chi,Zhigang Sun,Xinwang Zhang,Zhihua Wang, A 0.1-6.0-GHz dual-path SDR transmitter supporting intraband carrier aggregation in 65-nm CMOS, IEEE Transactions on Very Large Scale Integration Systems, Vol.23, No.5, pp. 944 - 957, 2015.

[4] Xinwang Zhang,,Baoyong Chi,Zhihua Wang, A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.62, No.4, pp. 1005 - 1014, 2015.

[5] Xinwang Zhang,Yichuang Sun,Zhihua Wang,Baoyong Chi, A 0.5–30GHz wideband differential CMOS T/R switch with independent bias and leakage cancellation techniques, ISCAS 2015, pp. 449 - 452, 2015.

[6] Feng Ma,Xinwang Zhang,Baoyong Chi, A 100M-1.5 GHz Harmonic-Rejection SDR Receiver Front-End, ASICON 2015, pp. 1 - 4, 2015.

[7] Siyang Han,Baoyong Chi,Xinwang Zhang,Zhihua Wang, A power scalable PLL frequency synthesizer for high-speed Δ-∑ ADC, Journal of Semiconductors, Vol.35, No.8, pp. 085002-1-6, 2014.

[8] Yang Xu,Zehong Zhang,Baoyong Chi,Qiongbing Liu,Xinwang Zhang,Zhihua Wang, Dual-mode 10MHz BW 4.8/6.3mW reconfigurable lowpass/complex bandpass CT ΣΔ modulator with 65.8/74.2dB DR for a zero/low-IF SDR receiver, RFIC 2014, pp. 313 – 316, 2014.

[9] Xinwang Zhang,Baoyong Chi,Bingqiao Liu,Zhihua Wang, -80dBm~0dBm dynamic range, 30mV/dB detection sensitivity piecewise RSSI for SDR/CR receivers, MWSCAS 2014, pp. 89 - 92, 2014.

[10] Xinwang Zhang,Zhihua Wang,Baoyong Chi, A 0.1-1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration, A-SSCC 2014, pp. 353 - 356, 2014.

[11] Xinwang Zhang,Yang Xu,Bingqiao Liu,Qian Yu,Siyang Han,Qiongbing Liu,Zehong Zhang,Yanqiang Gao,Zhihua Wang, Baoyong Chi, A 0.1-5GHz flexible SDR receiver in 65nm CMOS, A-SSCC 2014, pp. 249 - 252, 2014.

[12] Xinwang Zhang,Baoyong Chi,Meng Cao,Ling Fu,Zhaokang Xia,Yun Yin,Hongxing Feng,Xing Zhang,Patrick Chiang, Zhihua Wang, A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS, Analog Integrated Circuits and Signal Processing, Vol.77, No.3, pp. 567 - 582, 2013.

[13] Zhaokang Xia,Xinwang Zhang,Baoyong Chi, A 0.1-4GHz Reconfigurable Multi-band CMOS LNA for SDR Applications, ICEICE 2012, pp. 5 - 8, 2012.

[14] Xinwang Zhang,Yun Yin,Meng Cao,Zhigang Sun,Ling Fu,Zhaokang Xia,Hongxing Feng,Xing Zhang,Baoyong Chi, Ming Xu, Zhihua Wang, A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS, CICC 2012, pp. 1 - 4, 2012.