题目/Title：A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA

作者/Author：张欣旺,池保勇,王志华
                        Xinwang Zhang,,Baoyong Chi,Zhihua Wang

期刊/Journal：IEEE Transactions on Circuits and Systems I: Regular Papers

年份/Issue Date：2015Apr.

卷（期）及页码/Volume（No.）&pages：Vol.62, No.4, pp. 1005 - 1014

摘要/Abstract：
A 0.1-1.5 GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8-phase LO generator, the highest oscillation frequency of the frequency synthesizer is reduced from four times to twice of the highest operation frequency. The power-scalable Class-AB fully-differential opamp with Miller feed-forward compensation and quasi-floating gate (QFG) technique is proposed to implement the low power blocker-resilient TIA. The HR receiver has been implemented in 65 nm CMOS. With 1.8 mm2 core chip area and 5.4-24.5 mA current consumption from a 1.2 V power supply, the receiver achieves 85 dB conversion gain, 4.3 dB NF, +13 dBm/ +14 dBm IB/OB-IIP3, >54/56 dB HR3/HR5 (30-40 dB improvement with the vector gain calibration), and 2.3% EVM for 32QAM modulation.