题目/Title：
                        A power scalable PLL frequency synthesizer for high-speed Δ-∑ ADC

作者/Author：
                        Siyang Han,Baoyong Chi,Xinwang Zhang,Zhihua Wang

期刊/Journal：半导体学报 Journal of Semiconductors

年份/Issue Date：2014.Aug.

卷（期）及页码/Volume（No.）&pages：Vol.35, No.8, pp. 085002-1-6

摘要/Abstract：

A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for Δ-∑ analog-to-digital converter (ADC) in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode (300-360 MHz) or in low-power mode (35-130 MHz) to satisfy the ADC's requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the frequency synthesizer achieves a phase-noise of -132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of -112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.