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Ni Xu

Biography

Enrollment Date: 2009

Graduation Date：2014

Degree：Ph.D.

Defense Date：2014.05.28

Advisors：Woogeun Rhee

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Study on Linear Phase Modulator Based on Phase-locked Loop

Abstract:
Compared with conventional transmitters, the polar transmitter consumes less power and area without requiring mixers, digital-to-analog converters (DACs) and low-pass-filters (LPFs). In addition, by utilizing phase and amplifier modulation individually, the power amplifier is able to work in the switch mode which improves the power efficiency a lot. The phase modulator is one of the key blocks in the transmitter and any non-ideal effects in the modulator will degrade the system performance directly. This dissertation is focusing on the linear phase modulator design based on the phase-locked loop (PLL) architecture. By analyzing the non-ideal effects in the phase modulation, several techniques are proposed to improve the performance. The proposed architecture is also implemented in CMOS for the system verification. Firstly, the principle of the  PLL is presented, including the working mechanism and filtering characteristic, which are the basic of the phase modulation. And then, the phase modulations with one-point and two-point methods are compared. The two-point modulation is chosen in this dissertation which is more suitable for the high data rate modulation. By modeling the two-point modulation, the non-ideal effects are analyzed and the recent researches on these issues are studied. In this work, three techniques are proposed to improve the performance of the two-point phase modulation. The hybrid-loop architecture is proposed for the phase modulation by employing a semi-digital  PLL. The semi-digital  PLL provides linear phase tracking and low-complexity design, while offering technology scalability and digital-assisted calibration capability without complex time-to-digital converter (TDC) design. A 1-bit high-pass modulation with FIR finite impulse response (FIR) filtering is proposed. The use of the dedicated 1-bit high-pass modulation path mitigates the nonlinearity problem of the digital controlled oscillator (DCO) gain in the two-point modulator design, which can substantially simplify the two-point modulator architecture while achieving good linearity. In addition, the hybrid FIR filtering method is employed for the low-pass modulation path to enhance linearity and reduce high frequency quantization noise. The hybrid-loop phase modulator with TDC-less semi-digitalPLL is implemented in 65 nm CMOS, consuming a 6.9 mW from a 1 V supply. When the 270.833 kb/s GMSK modulation is applied, the proposed hybrid modulator meets the spectrum mask requirement for GSM standards with 3.5 dB margin at 400 kHz offset frequency. A 1.8 GHz 1.08 Mb/s GMSK/GFSK hybrid-loop two-point modulator based on the TDC-less semi-digitalPLL has been implemented in 65 nm CMOS. At the divide-by-2 output frequency of 913.2 MHz, the error-vector-magnitude (EVM) values of 1.79% and 1.63% are achieved with 1.08 Mb/s and 270 kb/s GMSK modulation respectively. When the 1.08 Mb/s GFSK modulation is performed with the same PLL parameters, the EVM value of 1.96% is achieved. The experimental results show that the proposed hybrid-loop architecture offers an alternative way of realizing digital modulation while avoiding the complicated design effort for the high performance TDC. The digital FIR filtering and the hybrid FIR filtering methods employed for the high-pass and low-pass modulation paths are shown to be useful to improve the modulation linearity and reduce the coupling effect. The testing results also prove that the use of the 1-bit high-pass modulation path achieves good linearity without complex calibration blocks.

Publications

Papers：：

[1] Sitao Lv,Ni Xu,Woogeun Rhee,Zhihua Wang, A Hybrid Frequency/Phase-Locked Loop for Versatile Clock Generation with Wide Reference Frequency Range, VLSI-DAT 2016, pp. 1 - 4, 2016.

[2] Ni Xu,Woogeun Rhee,Zhihua Wang, A 2 GHz 2 Mb/s Semi-Digital 2+-Point Modulator With Separate FIR-Embedded 1-Bit DCO Modulation in 0.18 μm CMOS, IEEE Microwave and Wireless Components Letters, Vol.25, No.4, pp. 253 - 255, 2015.

[3] Ni Xu,Sitao Lv,Woogeun Rhee,Zhihua Wang, A digital-intensive F/PLL-based two-point modulator with a constant-gain DCO for linear FMCW generation, RFIT 2015, pp. 193 - 195, 2015.

[4] Xiaoyong Li,Sitao Lv,Xiaofeng Liu,Ni Xu,Woogeun Rhee,Wen Jia,Zhihua Wang, A 10 Mb/s Hybrid Two-Point Modulator with Front-End Phase Selection and Dual-Path DCO Modulation, IWS 2015, pp. 1 - 4, 2015.

[5] Jun Li,Ni Xu,Yuanfeng Sun,Rhee,W.,Zhihua Wang, A 6.5mW, wide band dual-path LC VCO design with mode switching technique in 130nm CMOS, IEEE SiRF 2015, pp. 7 - 10, 2015.

[6] Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Ni Xu,Woogeun Rhee,Liji Wu,Chun Zhang, A 4.8-mW/Gb/s 9.6-Gb/s 5+1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.61, No.4, pp. 209 - 213, 2014.

[7] Ni Xu,Woogeun Rhee,Zhihua Wang, A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation, IEEE Journal of Solid-State Circuits, Vol.49, No.10, pp. 2172 - 2186, 2014.

[8] Yanfeng Li,Ni Xu,Woogeun Rhee,Zhihua Wang, A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL, ISCAS 2014, pp. 1440 - 1443, 2014.

[9] Yang Li,Ni Xu,Yining Zhang,Wooguen Rhee,Sanghoon Kang,Zhihua Wang, A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications, A-SSCC 2014, pp. 261 - 264 , 2014.

[10] Woogeun Rhee,Ni Xu,Bo Zhou,Zhihua Wang, Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design, Journal of Semiconductor Technology and Science, Vol.13, No.2, pp. 170 - 183, 2013.

[11] Y. Han,D. Lin,Shuli Geng,Ni Xu,Woogeun Rhee,T-Y Oh,Zhihua Wang, All-digital PLL with ΔΣ DLL embedded TDC, Electronics Letters, Vol.49, No.2, pp. 93 - 94, 2013.

[12] Shuli Geng,Ni Xu,Jun Li,Xueyi Yu,Woogeun Rhee,Zhihua Wang, A PLL/DLL Based CDR with Delta-Sigma Frequency Tracking and Low Algorithmic Jitter Generation, ISCAS 2013, pp. 1179 - 1182, 2013.

[13] Nan Qi,Yang Xu,Baoyong Chi,Yang Xu,Xiaobao Yu,Xing Zhang,Ni Xu,Patrick Chiang,Woogeun Rhee, Zhihua Wang, A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration, IEEE Transactions on Circuits and Systems -I: Regular papers, Vol.59, No.8, pp. 1720 - 1732, 2012.

[14] Yuanfeng Sun,Zhuo Zhang,Ni Xu,Min Wang,Woogeun Rhee,Tae-Young Oh,Zhihua Wang, A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control, IEEE Microwave and Wireless Components Letters, Vol.22, No.12, pp. 654 - 656, 2012.

[15] Yuanfeng Sun,Jun Li,Zhuo Zhang,Min Wang,Ni Xu,Hang Lv,Woogeun Rhee,Yongming Li,Zhihua Wang, A 2.74–5.37GHz boosted-gain type-I PLL with <15% loop filter area, RFIC 2012, pp. 181 - 184, 2012.

[16] Ke Huang,Chen Jia,Xuqiang Zheng,Ni Xu,Chun Zhang,Woogeun Rhee,Zhihua Wang, A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology, ISCAS 2012, pp. 313 - 316, 2012.

[17] Deyuan Lin,Ni Xu,Woogeun Rhee,Zhihua Wang, An 11.7–17.2GHz digitally-controlled oscillator in 65nm CMOS for high-band UWB applications, ICSICT 2012, pp. 1 - 3, 2012.

[18] Ni Xu,Woogeun Rhee,Zhihua Wang, Semidigital PLL design for low-cost low-power clock generation, Journal of Electrical and Computer Engineering, Vol.2011, pp. 1 - 9, 2011.

[19] Ni Xu,Zhuo Zhang,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, Technology-Friendly Phase-Locked Loops, MWSCAS 2011, pp. 1 - 4, 2011.

[20] Jun Li,Ni Xu,Woogeun Rhee,Zhihua Wang, A -131dBc@1M PhaseNoise, 74% Spectral Efficiency, GA optimized FIR impulse radio UWB transmitter, PrimeAsia 2010, pp. 384 - 387, 2010.

[21] Woogeun Rhee,Ni Xu,Bo Zhou,Zhihua Wang, Low Power, Non Invasive UWB Systems for WBAN and Biomedical Applications, ICTC 2010, pp. 35 - 40, 2010.

[22] Jun Li,Ni Xu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, Reconfigurable, Fast AFC Technique Using Code Estimation and Binary Search Algorithm for 0.2-6GHz Software-Defined Radio Frequency Synthesis, APCCAS 2010, pp. 1135 - 1138, 2010.