Fangxu Lv

Biography

Enrollment Date : 2014

Anticipated Graduation Date：2019

Type of Candidate：Ph.D. Candidate

Advisors：Zhihua Wang

Department：Institute of Microelectronics，Tsinghua University

Research Area：

Publications

Papers：

[1] Xuqiang Zheng,Fangxu Lv,Lei Zhou,Danyu Wu,Jin Wu,Chun Zhang,Woogeun Rhee,Xinyu Liu, Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators, IEEE Journal of Solid-State Circuits, Vol.55, No.6, pp. 1651 - 1664, 2020.

[2] Fangxu Lv,Jianye Wang,Xuqiang Zheng,Ziqiang Wang,Yajun He,Hao Ding,Yongcong Liu,Chun Zhang,Zhihua Wang, A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65nm CMOS Technology, Journal of Harbin Institute of Technology (New Series), Vol.26, No.3, pp. 50-57, 2019.

[3] Fangxu Lv,Xuqiang Zheng,Jianye Wang,Guoli Zhang,Ziqiang Wang,Shuai Yuan,Yajun He,Chun Zhang,Zhihua Wang, A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology, Analog Integrated Circuits and Signal Processing, Vol.99, No.1, pp. 147 - 157, 2019.

[4] Dengjie Wang,Hong Chen,Wenhuan Luan,Xin Lin,Fangxu Lv,Ziqiang Wang,Hanjun Jiang,Chun Zhang,Zhihua Wang, A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology, MWSCAS 2019, pp. 251 - 254, 2019.

[5] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shuai Yuan,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang, A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS, IEEE Journal of Solid-State Circuits, Vol.52, No.11, pp. 2963 - 2978, 2017.

[6] Yajun He,Ziqiang Wang,Han Liu,Fangxu Lv,Shuai Yuan,Chun Zhang,Zhihua Wang,Hanjun Jiang, An 8.5–12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes, MWSCAS 2017, pp. 791 - 794, 2017.

[7] Fangxu Lv,Xuqiang Zheng,Shuai Yuan,Ziqiang Wang,Yajun He,Chun Zhang,Zhihua Wang,Fangxu Lv,Jianye Wang, A 40-80Gb/s PAM4 Wireline Transmitter in 65nm CMOS Technology, MWSCAS 2017, pp. 539 - 542, 2017.

[8] Shuai Yuan,Ziqiang Wang,Yajun He,Fangxu Lv,Chun Zhang,Zhihua Wang,Hanjun Jiang, A 1.25–12.5Gb/s 5.28mW/Gb/s multi-standard serial-link transceiver with 32dB of equalization in 40nm CMOS, EDSSC 2017, pp. 1 - 2, 2017.

[9] Yajun He,Ziqiang Wang,Han Liu,Fangxu Lv,Shuai Yuan,Chun Zhang,Xiang Xie,Hanjun Jiang, An 8.5-12.5GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes, EDSSC 2017, pp. 1 - 2, 2017.

[10] Fangxu Lv,Jianye Wang,Heming Wang,Ziqiang Wang,Yajun He,Yongcong Liu,Chun Zhang,Zhihua Wang,Hanjun Jiang, A 10 GHz Ring-VCO Based Injection-Locked Clock Multiplier for 40 Gb/s SerDes Application in 65 nm CMOS Technology, EDSSC 2017, pp. 1 - 2, 2017.

[11] Fangxu Lv,Xuqiang Zheng,Ziqiang Wang,Yajun He,Chun Zhang,Jianye Wang,Zhihua Wang,Hanjun Jiang, Design of 80-Gb/s PAM4 Wireline Receiver in 65-nm CMOS Technology, EDSSC 2017, pp. 1 - 2, 2017.

[12] Fangxu Lv,Jianye Wang,Xuqiang Zheng,Shuai Yuan,Ziqiang Wang,Yajun He,Zhihua Wang,Hanjun Jiang, A 10–60 Gb/s wireline transmitter with a 4-tap multiple-MUX based FFE, EDSSC 2017, pp. 1 - 2, 2017.

[13] Xuqiang Zheng,Fangxu Lv,Feng Zhao,Shigang Yue,Chun Zhang,Ziqiang Wang,Fule Li,Hanjun Jiang,Zhihua Wang, A 10 GHz 56 fsrms-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS, CICC 2017, pp. 1 - 4, 2017.

[14] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shigang Yue,Ziqiang Wang,Fule Li,Hanjun Jiang,Zhihua Wang, A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS, CICC 2017, pp. 1 - 4, 2017.

[15] Fangxu Lv,Jianye Wang,Dengjie Wang,Yongcong Liu,Ziqiang Wang, Design of 56 Gb/s PAM4 Wire-line Receiver With Ring VCO Based CDR in a 65 nm CMOS Technology, ASICON 2017, pp. 537 - 540, 2017.

[16] Naiwen Zhou,Ke Huang,Fangxu Lv,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 76 mW 40-Gb/s SerDes Transmitter With 64:1 MUX In 65-nm CMOS Technology, ICEIEC 2016, pp. 155 - 158, 2016.

[17] Xuqiang Zheng,Chun Zhang,Fangxu Lv,Feng Zhao,Shigang Yue,Ziqiang Wang,Fule Li,Zhihua Wang, A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS , ESSCIRC 2016, pp. 305 - 308, 2016.