题目/Title：Design of 56 Gb/s PAM4 Wire-line Receiver With Ring VCO Based CDR in a 65 nm CMOS Technology

作者/Author：
                        Fangxu Lv,Jianye Wang,Dengjie Wang,Yongcong Liu,Ziqiang Wang

会议/Conference：ASICON 2017

地点/Location：Guiyang, China

年份/Issue Date：2017.25-28 Oct.

页码/pages：pp. 537 - 540

摘要/Abstract：
This paper presents a 56 Gb/s 4-level pulse amplitude modulation (PAM4) wire-line receiver, which employs a quarter rate architecture. By employing a ring voltage control oscillator (VCO) based clock and data recovery (CDR) with separate proportional path, the complexity, power consumption and area can all be reduced. To reduce the noise of the detector and improve the stability of the CDR, both the major and minor transitions with the central crossover point are utilized to extract the phase error. The receiver is designed in a 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed PAM4 receiver can work at 56 Gb/s with 76 mW consumption.