Enrollment Date : 2015
Anticipated Graduation Date：2020
Type of Candidate：Ph.D. Candidate
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Research Area：
[1] Meng Ni,Xiao Wang,Fule Li,Zhihua Wang, A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.29, No.7, pp.1416-1427, 2021.
[2] Meng Ni,Xiao Wang,Fule Li,Woogeun Rhee,Zhihua Wang, A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.PP, No.99, pp.1-14, 2021.
[3] Peilin Yang,Xiao Wang,Chengwei Wang,Fule Li,Hanjun Jiang,Zhihua Wang, A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.28, No.9, pp. 2004 - 2013, 2020.
[4] Xiao Wang,Fule Li,Zhihua Wang, A Simple Histogram-based Capacitor Mismatch Calibration in SAR ADCs, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.PP, No.99, pp. 1 - 1, 2020.
[5] Meng Ni,Xiao Wang,Zhe Zhou,Yang Ding,Fule Li,Woogeun Rhee,Zhihua Wang, A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC, MWSCAS 2020, pp. 345 - 348, 2020.
[6] Meng Ni,Xiao Wang,Zhe Zhou,Yang Ding,Fule Li,Woogeun Rhee,Zhihua Wang, A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique, MWSCAS 2020, pp. 341 - 344, 2020.
[7] Xiao Wang,Fule Li,Wen Jia,Zhihua Wang, A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.66, No.3, pp. 322 - 326, 2019.
[8] Chengwei Wang,Xiao Wang,Yang Ding,Fule Li,Zhihua Wang, A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique, ISCAS 2018, pp. 1 - 5, 2018.
[9] Xiao Wang,Chengwei Wang,Fule Li,Zhihua Wang, A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process, ISCAS 2018, pp. 1 - 5, 2018.
[10] Nan Qi,Fan Chen,Lingwei Zhang,Xiaoman Wang,Baoyong Chi, A Reconfigurable Multi-Mode Multi-band Transmitter with Integrated Frequency Synthesizer for Short-Range Wireless Communication, Journal of Semiconductors, Vol.34, No.9, pp. 095008-1-7, 2013.
[11] Qiuling Zhu,Chun Zhang,Xiaohui Wang,Zhongqi Liu,Yongmin Li,Zhihua Wang, ASIC Implementation of Low Power Baseband Processor for UHF RFID Tag, Semiconductor Technology, Vol.34, No.2, pp. 172 - 176, 2009.
[12] Xiaohui Wang,Chun Zhang,Changming Ma,Xinjun Wu, Low power Design of an UHF RFID Baseband Processor, Semiconductor Technology, Vol.34, No.5, pp. 502 - 505, 2009.
[13] Qiuling Zhu,Chun Zhang,Xiaohui Wang,Ziqiang Wang,Fule Li,Zhihua Wang, VLSI Design of Spread Spectrum Encoding Low Power RFID Tag Baseband Processor, VLSI-DAT 2009, pp. 191 – 194, 2009.
[1] Fule Li, Yang Ding, Xiao Wang. Broadband low-power-consumption comparator circuit: China, 202010403259.6[P]. 2022-4-15.
[2] Fule Li, Xiao Wang, Wen Jia, Zhihua Wang. Pipelined analog-to-digital converter as well as operational amplifier adaptive configuration circuit and method thereof: China, 201710326116.8[P]. 2022-04-01.