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Yuanfeng Sun

Biography

Enrollment Date: 2005

Graduation Date：2010

Degree：Ph.D.

Defense Date：2010.12.21

Advisors：Zhihua Wang

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Study on Dual-Path Control Techniques for Phase-locked Loop

Abstract:
A PLL (Phase-Locked Loop) frequency synthesizer is one of the key building blocks in the transceiver to determine the overall noise performance, and it has been widely used in modern wireless and wireline applications. Designing frequency synthesizer with low noise, low spur, low cost and broad tuning range is critical for many standards. The main research items and achievements of this dissertation are as follow: A dual-path control technique is proposed. The dual-path PLL exhibits a small control voltage range in the loop filter, resulting in improved charge pump linearity. Also, the VCO gain variation can be little since the tuning voltage of the fine-tuning varactor is near the middle of the tuning curve. The dual-path PLL can achieve low in-band noise and constant PLL bandwidth. A dynamic bandwidth control method for dual-path PLL is proposed. The settling process can be divided into two continous mode. During the transient mode, the coarse-tuning bandwidth is widened so that frequency acquisition is dominated by the high gain coarse-tuning loop. During normal mode, fine-tuniing loop is dominated with narrow bandwidth and achieves phase locked. It offers an effective way for dual-path PLL to achieve fast settling time. The design method and architecture selection of VCO (Voltage-Controlled Oscillator) are analyzed. A 52% tuning range VCO is implemented in 180nm CMOS process for WCDMA/HSDPA. Additionally, A dual-path VCO is implemented in 65nm CMOS process for GSM/EDGE application, and it exhibits -120.7dBc/Hz at a 400 kHz offset from a 1.73 GHz carrier, showing better performance than the conventional single-path VCO that is implemented for comparison. A dual-path ΔΣ fractional-N PLL is implemented in 65nm CMOS, and exhibits nearly -100dBc/Hz in-band noise contribution and –72.4dBc out-band fractional spur performances from a 1.8GHz carrier. With proposed dynamic bandwidth control method, the dual-path PLL is implemented in 90nm CMOS process. The PLL can achieve about 95% settling time reduction. Applying dual-path control technique, a low cost type-I PLL architecture having much smaller loop filter area is designed, and the PLL exhibits quasi type-II performance. The 65% wide tuing range type-I dual-path PLL is implemented in 130nm CMOS process. The dual-path quasi type-II architecture can achieve about 25dB and 10dB reference spur compensation at low frequency band (2.765GHz) and high band (5.04GHz), repectively. The area of loop filter is only 12.6% of the active core. Semi-digital dual-path architecture is proposed, and digital coarse-tuning loop design is analyzed. A 2 GHz PLL is implemented in 180nm CMOS process, and it exhibits less than +/–3.5% bandwidth variation and less than 2dB in-band noise variation over entire tuning range. It can also offer seamless tuning capability for VCO frequency drift due to temperature variation.

Publications

Papers：：

[1] Jun Li,Ni Xu,Yuanfeng Sun,Rhee,W.,Zhihua Wang, A 6.5mW, wide band dual-path LC VCO design with mode switching technique in 130nm CMOS, IEEE SiRF 2015, pp. 7 - 10, 2015.

[2] Yuanfeng Sun,Zhuo Zhang,Ni Xu,Min Wang,Woogeun Rhee,Tae-Young Oh,Zhihua Wang, A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control, IEEE Microwave and Wireless Components Letters, Vol.22, No.12, pp. 654 - 656, 2012.

[3] Yuanfeng Sun,Jun Li,Zhuo Zhang,Min Wang,Ni Xu,Hang Lv,Woogeun Rhee,Yongming Li,Zhihua Wang, A 2.74–5.37GHz boosted-gain type-I PLL with <15% loop filter area, RFIC 2012, pp. 181 - 184, 2012.

[4] Yuanfeng Sun,Jian Qiao,Xueyi Yu,Woogeun Rhee,Byeong-Ha Park,Zhihua Wang, A continuously tunable hybrid LC-VCO PLL with mixed-mode dual-path control and bi-level delta-sigma modulated coarse tuning, IEEE Transactions on Circuits and Systems I-Regular Papers, Vol.58, No.9, pp. 2149 - 2158, 2011.

[5] Jun Li,Bo Zhou,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, Reconfigurable, Spectrally Efficient, High Data Rate IR-UWB Transmitter Design Using a Δ–Σ PLL Driven ILO and a 7-Tap FIR Filter, VLSI-DAT 2011, pp. 1 - 4, 2011.

[6] Ni Xu,Zhuo Zhang,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, Technology-Friendly Phase-Locked Loops, MWSCAS 2011, pp. 1 - 4, 2011.

[7] Yuanfeng Sun,Xueyi Yu,Woogeun Rhee,Sangsoo Ko,Wooseung Choo,Byeong-Ha Park,Zhihua Wang, Dual-Path LC VCO Design With Partitioned Coarse-Tuning Control in 65 nm CMOS, IEEE Microwave and Wireless Components Letters, Vol.20, No.3, pp. 169 - 171 , 2010.

[8] Yuanfeng Sun,Xueyi Yu,Woogeun Rhee,Dawn Wang,Zhihua Wang, A Fast Settling Dual-Path Fractional-N PLL With Hybrid-Mode Dynamic Bandwidth Control, IEEE Microwave and Wireless Components Letters, Vol.20, No.8, pp. 462 - 464, 2010.

[9] Yuanfeng Sun,Xueyi Yu,Woogeun Rhee,Sangsoo Ko,Wooseung Choo,Byeong-Ha Park,Zhihua Wang, Low-Noise Fractional-N PLL Design with Mixed-Mode Triple-Input LC VCO in 65nm CMOS, RFIC 2010, pp. 61 - 64, 2010.

[10] Zhuo Zhang,Jun Li,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, A Digitally Reconfigurable Auto Amplitude Calibration Method for Wide Tuning Range VCO Design, ICSICT 2010, pp. 542 - 544, 2010.

[11] Jun Li,Ni Xu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, Reconfigurable, Fast AFC Technique Using Code Estimation and Binary Search Algorithm for 0.2-6GHz Software-Defined Radio Frequency Synthesis, APCCAS 2010, pp. 1135 - 1138, 2010.

[12] Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang, An FIR-embedded noise filtering method for ΔΣ fractional-N PLL clock generators, IEEE Journal of Solid-State Circuits, Vol.44, No.9, pp. 2426 - 2436, 2009.

[13] Li Zhang,Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Wang, D.,Zhihua Wang,Hongyi Chen, A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops, IEEE Journal of Solid-State Circuits, Vol.44, No.11, pp. 2922 - 2934, 2009.

[14] Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Hyung Ki Ahn,Byeong-Ha Park,Zhihua Wang, A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications, IEEE Journal of Solid-State Circuits, Vol.44, No.8, pp. 2193 - 2201, 2009.

[15] Yuanfeng Sun,Jian Qiao,Jun Li,Rui He,Chengwen Liu,Woogeun Rhee,Sung Hun Woo,Zhihua Wang, A Low-Cost, Multi-Standard ΔΣ Fractional-N Synthesizer Design for WiMAX/WLAN Applications, ISOCC 2009, pp. 100 - 103, 2009.

[16] Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Sangsoo Ko,Wooseung Choo,Byeong-Ha Park,Zhihua Wang, A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order ΔΣ modulation and weighted FIR filtering, A-SSCC 2009, pp. 77 - 80, 2009.

[17] Xueyi Yu,Yuanfeng Sun,Li Zhang,Woogeun Rhee,Zhihua Wang, A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering, ISSCC 2008, pp. 346 - 347. , 2008.

[18] Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang,Hyung Ki Ahn,Byeong-Ha Park, A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications, CICC 2008, pp. 753 - 756, 2008.

[19] Li Zhang,Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang,Hongyi Chen,Wang, D., A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops, A-SSCC 2008, pp. 417 - 420, 2008.