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Liyuan Liu

Biography

Enrollment Date: 2005

Graduation Date：2010

Degree：Ph.D.

Defense Date：2010.06.12

Advisors：Shaojun Wei Zhihua Wang Dongmei Li

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Low Voltage and Low Power Techniques for High Precision Audio ΔΣ Modulator

Abstract:
With continuous development of the integrated circuits technology and its ever widening applications, System-on-Chip (SoC) has become the design mainstream. Analog-to-digital conveter (A/D) which is an indispensable building block in SoC has been paid more attention to. The A/D based on ΔΣ modulator plays an important role in the high dynamic range signal processing SoCs. The scaling down of the feature size as well as the supply voltage together with rigorous demand of low power has brought many difficulties to such converter design. Focusing on the high precision ΔΣ modulator design under low voltage and low power conditions, this dissertation has following achievements which are valuable to the implementation of high precision A/D and correspondence SoCs. The principle of ΔΣ modulator is presented. We study kinds of modulator architectures and choose feed forward topology combined with multi-bit quantizer. This topology can effectively suppress the integrators’ swing and relax the gain requirement of OTA. The non-ideal effects which limit the modulator performance are analyzed. We emphasize on the quantization noise mixture effect induced by non-linear OTA gain. This effect greatly raised the noise floor in the signal band and becomes one of the most important performance limitation factors. Under low supply voltage, we can mitigate this effect by fining the quantization step in the multi-bit quantizer. A modulator with 24 kHz bandwidth under 1V is fabricated in 0.18μm CMOS which adopts feed forward topology combined with flash quantizer. Measurement shows with around 42dB dc gain of the OTA in the first integrator, the peak SNDR of 91.5dB can be achieved, and the power consumption is only 663μW. We propose a kind of successive approximation quantizer with asynchronous timing control logic. There is only one comparator and hence the area cost and power consumption of the quantizer is reduced. Another advantage is its excellent tolerance to the comparator offset voltage. Dynamic comparator with no static power can be employed. A modulator with digital feed forward and successive approximation quantizer is implemented in 0.18μm CMOS. The modulator achieves 92dB peak SNDR under 1V across 24 kHz bandwidth. The power consumption is only 350μW

Publications

Papers：：

[1] Yunqi Yang, Ming Zhong, Qianli Ma, Ziyi Lin, Leliang Li, Guike Li, Liyuan Liu, Jian Liu, Nanjian Wu, Haikun Jia, Xinghui Liu, Nan Qi, A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O, ICTA 2022, pp.202-203, 2022.

[2] Cong Shi,Jie Yang,Ye Han,Zhongxiang Cao,Qi Qin,Liyuan Liu,Nan-Jian Wu,Zhihua Wang, A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network, IEEE Journal of Solid-State Circuits, Vol.49, No.9, pp. 2067 - 2082, 2014.

[3] Cong Shi,Jie Yang,Ye Han,Zhongxiang Cao,Qi Qin,Liyuan Liu,Nanjian Wu,Zhihua Wang, A 1000fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array and Self-Organizing Map Neural Network, ISSCC 2014, pp. 128 - 129, 2014.

[4] Lingwei Zhang,Baoyong Chi,Nan Qi,Liyuan Liu,Hanjun Jiang,Zhihua Wang, A Lower Power Reconfigurable Multi-Band Transceiver for Short-Range Communication, Journal of Semiconductors, Vol.34, No.3, pp. 035008-1-7 , 2013.

[5] Liyuan Liu,Dongmei Li,Zhihua Wang, A 0.6-V to 1-V audio ΔΣ modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V, Journal VLSI Design, Vol.2013, Article ID 353080, 2013.

[6] Yan Feng,Libing Zhou,Liyuan Liu,Dongmei Li, A 2GSPS 6-bit Two-Channel-Interleaved Successive Approximation ADC, ICCIS 2013, pp. 1640 - 1643, 2013.

[7] Xiaodan Xiong,Chenxi Han,Qing Ding,Lyuan Liu,Dongmei Li, A Parallel Delta-sigma ADC Based on Compressive Sensing, EDSSC 2013, pp. 1 - 2, 2013.

[8] Liyuan Liu,Dongmei Li,Liangdong Chen,Zhihua Wang, A 1-V 15-Bit Audio ΔΣ-ADC in 0.18μm CMOS, IEEE Transactions on Circuits and Systems I-Regular Papers, Vol.59, No.5, pp. 915 - 925, 2012.

[9] Hui Jiang,Ziqiang Wang,Liyuan Liu,Chun Zhang,Zhihua Wang, A Combined Low Power SAR Capacitance-to-Digital/Analog-to-Digital Converter for Multisensory System, MWSCAS 2012, pp. 1000 - 1003, 2012.

[10] Yafei Ye,Liyuan Liu,Jiangyuan Li,Dongmei Li,Zhihua Wang, A 120dB SNDR Audio Sigma-Delta Modulator with an Asynchronous SAR Quantizer, ISCAS 2012, pp. 2357 - 2360, 2012.

[11] Liyuan Liu,Dongmei Li,Yafei Ye,Zhihua Wang, Analysis and simulation of a 2nd order ΔΣ modulator with single-comparator multi-bit quantizer, RFIT 2011, pp. 189 - 192, 2011.

[12] Libing Zhou,Liyuan Liu,Dongmei Li, A Calibration Technique for Mismatch of Capacitor Arrays in A/D and D/A converters, PrimeAsia 2011, pp. 5 - 8, 2011.

[13] Yiwei Zhang,Liyuan Liu,Dongmei Li, A 3.3V to 3.19V Low-Dropout Regulator with frequency compensation strategy without trimming, PrimeAsia 2011, pp. 17 - 20 , 2011.

[14] Yafei Ye,Ting Li,Zhihua Wang,Liyuan Liu,Dongmei Li, A hardware-effective digital decimation filter implementation for 24-bit ΔΣ ADC, PrimeAsia 2011, pp. 13 - 16, 2011.

[15] Binjie Zhu,Hanjun Jiang,Liyuan Liu,Jigang Shao,Liwei Deng,Fule Li,Chun Zhang,Zhihua Wang, A Wireless SoC for Alimentary Canal pH Value Continuously Monitoring, MWSCAS 2011, pp. 1 - 4, 2011.

[16] Liyuan Liu,Dongmei Li,Yafei Ye,Zhihua Wang, A 92.4dB SNDR 24kHz ΔΣ modulator consuming 352μW, ISLPED 2011, pp. 351 - 356, 2011.

[17] Liyuan Liu,Dongmei Li,Liangdong Chen,Yafei Ye,Zhihua Wang, A 1V 15-bit Audio ΔΣ ADC in 0.18µm CMOS, ISCAS 2011, pp. 510 - 513, 2011.

[18] Pengpeng Yuan,Zhihua Wang,Dongmei Li,A. Wang,Liyuan Liu, A Nanopower CMOS Bandgap Reference with 30ppm/degree C from -30 degree C to 150 degree C, ISCAS 2011, pp. 2285 - 2288, 2011.

[19] Liyuan Liu,Dongmei Li,Yafei Ye,Liangdong Chen,Zhihua Wang, A 95dB SNDR audio ΔΣ modulator in 65nm CMOS, CICC 2011, pp. 1 - 4, 2011.

[20] Yafei Ye,Liyuan Liu,Fule Li,Dongmei Li,Zhihua Wang, An 8-bit 1MHz Successive Approximation Register (SAR) A/D with 7.98 ENOB, ASID 2011, pp. 139 - 142, 2011.

[21] Peng Li,Liyuan Liu,Dongmei Li, Design of a Comparator with High Speed and High Precision, Semiconductor Technology, Vol.35, No.10, pp. 1011 - 1015, 2010.

[22] Jinxiong Wang,Liyuan Liu,Dongmei Li, High-Gain and Wide Bandwidth Gain-Boosting OTA, Semiconductor Technology, Vol.35, No.10, pp. 1007 - 1010, 2010.

[23] Jinxiong Wang,Liyuan Liu,Dongmei Li, A High Linearity 14-Bit 40 MS/s Pipelined A/D Converter, Microelectronics, Vol.40, No.6, pp. 765 - 773, 2010.

[24] Hao Chen,Liyuan Liu,Dongmei Li,Chun Zhang,Zhihua Wang, A 12-bit current steering DAC with 2-dimensional gradient-error tolerant switching scheme, Chinese Journal of Semiconductors, Vol.31, No.10, pp. 105006-1-6, 2010.

[25] Liyuan Liu,Dongmei Li,Liangdong Chen,Chun Zhang,Shaojun Wei,Zhihua Wang, A low power 8-bit successive approximation register A/D for a wireless body sensor node, Chinese Journal of Semiconductors, Vol.31, No.6, pp. 0650041 - 0650045, 2010.

[26] Liyuan Liu,Liangdong Chen,Dongmei Li,Zhihua Wang,Shaojun Wei, A 1.1 mW 87 dB dynamic range ΔΣ modulator for audio applications, Chinese Journal of Semiconductors, Vol.31, No.5, pp. 0550031 - 0550037, 2010.

[27] Liyuan Liu,Dongmei Li,Liangdong Chen,Chun Zhang,Shaojun Wei,Zhihua Wang, A 1V 663μW 15-bit Audio ΔΣ Modulator in 0.18μm CMOS, VLSI-DAT 2010, pp. 194 - 197, 2010.

[28] Liangdong Chen,Liyuan Liu,Dongmei Li,Chun Zhang,Zhihua Wang, A 1V 210µW 98dB SFDR Audio ΔΣ Modulator in 180nm Standard CMOS, ICSICT 2010, pp. 379 - 381, 2010.

[29] Xiaoliang Yao,Liyuan Liu,Dongmei Li,Liangdong Chen,Zhihua Wang, A 90dB DR audio delta-sigma DAC with headphone driver for hearing aid, CISP 2010, pp. 2890 - 2893, 2010.

[30] Liyuan Liu,Dongmei Li,Liangdong Chen,Chun Zhang,Shaojun Wei,Zhihua Wang, A 1V 350μW 92dB SNDR 24 kHz ΔΣ modulator in 0.18μm CMOS, A-SSCC 2010, pp. 1 - 4, 2010.

[31] Yingjia Zhu,Liyuan Liu,Dongmei Li, A two phase non-overlap clock generator with independent pulse width adjusting, Semiconductor Technology, Vol.34, No.10, pp. 1032 - 1035, 2009.

[32] Yingjia Zhu,Liyuan Liu,Dongmei Li, A high linearity 100kHz signal bandwidth ΣΔ modulator, Microelectronics, Vol.39, No.5, pp. 610 - 614, 2009.

[33] Yingjia Zhu,Liyuan Liu,Dongmei Li, A 100 kHz Signal Bandwidth ∑-△ Modulator with High Linearity, Microelectronics, Vol.39, No.5, pp. 610 - 614, 2009.

[34] Jianguo Pang,Liyuan Liu,Dongmei Li, Digital Sine-Wave Generator for Testing High Resolution DAC, Microelectronics, Vol.39, No.4, pp. 470 - 473, 2009.

[35] Yingjia Zhu,Liyuan Liu,Dongmei Li, An 11 mW 79 dB DR △Σ modulator for ADSL applications, Chinese Journal of Semiconductors, Vol.30, No.10, pp. 105003-1-5, 2009.

[36] Jingyi Guo,Dongmei Li,Liyuan Liu,Fule Li, The hardware realization of a digital background calibration technique for pipelined A/D converters, Chinese High Technology Letters, Vol.19, No.3, pp. 290 - 294, 2009.

[37] Liyuan Liu,Liangdong Chen,Dongmei Li,Zhihua Wang,Shaojun Wei, A 1.1mW 87dB dynamic range audio ΔΣ modulator in 0.18µm CMOS, PrimeAsia 2009, pp. 17 - 20, 2009.

[38] Sen Lao,Liyuan Liu,Yingjia Zhu,Dongmei Li, Design and Realization of a 1.8 V Σ-Δ Modulator for Audio Application, Microelectronics, Vol.38, No.2, pp. 226 - 230, 2008.

[39] Chao Sun,Dongmei Li,Liyuan Liu,Fule Li, A 14-Bit 20 MS/s CMOS Pipelined A/D Converter, Microelectronics, Vol.38, No.3, pp. 320 - 325, 2008.

[40] Run Chen,Liyuan Liu,Dongmei Li, A Novel Multi-Stage Interpolation Filter Design Technique for High-Resolution Σ-Δ DAC, Chinese Journal of Semiconductors, Vol.28, No.11, pp. 1735 - 1741, 2007.

[41] Run Chen,Liyuan Liu,Dongmei Li,Zhihua Wang, Full custom design of a three-stage amplifier with 5500MHz•pF/mW Performance in 0.18 μm CMOS, VLSI-SoC 2007, pp. 242 - 247, 2007.

[42] Liyuan Liu,Run Chen,Dongmei Li, A 20-Bit Sigma-Delta D/A for Audio Applications in 0.13um CMOS, ISCAS 2007, pp. 3622 - 3625, 2007.

[43] Jingbo Duan,Fule Li,Liyuan Liu,Dongmei Li,Yongmin Li,Zhihua Wang, A pipelined A/D conversion technique with low INL and DNL, ISCAS 2007, pp. 3391 - 3394, 2007.

[44] Run Chen,Liyuan Liu,Dongmei Li, A cost-effective digital front-end realization for 20-bit ΣΔ DAC in 0.13 μm CMOS, CICC 2007, pp. 447 - 450, 2007.