Biography

Enrollment Date: 2014

Graduation Date：2017

Degree：M.S.

Defense Date：2017.05.25

Advisors：Woogeun Rhee

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Robust, Low Power DPLL Design

Abstract:
Dynamic voltage scaling (DVS) is a viable solution for energy-efficient mobile SOC (System on Chip) design and considered one of the most effective ways in reducing both switching and leakage power consumption. However, robust clock generation is challenging with an adaptive supply. For that reason, a separate regulator with higher supply voltage is often reserved for the phase-locked loop (PLL) in many systems. In the conventional digital intensive PLL, the time resolution of the single-ended TDC (Time to Digital Converter) is highly sensitive to supply voltage, resulting in inconsistent in-band noise and spur performance over supply voltage variation. The 1-bit TDC, namely, the bang-bang phase detector (BBPD) achieves robust phase detection under the low supply. Combined with the ring DCO, the bang-bang DPLL (BB-DPLL) enables an ultra-low voltage design but suffers from serious in-band noise degradation when it operates in a Fractional-N mode. The digital-to-time converter is employed to overcome the nonlinear property of the BBPD by minimizing the phase error at the input of the BBPD. Even though the 1-bit TDC is used, the performance is now limited by the DTC (Digital to Time Converter) linearity since a wide dynamic range of the DTC requires elaborate design efforts to achieve >10-bit linearity. Since the DTC design is based on the inverters and the programmable capacitor array, the DTC performance over PVT variations and supply noise coupling would be a concern. In this thesis, we propose a new DPLL structure, a hybrid finite-impulse response filter and delay compensation are employed to mitigate the phase-folding problem caused by nonlinearity of the BBPD. The DPLL is designed to operate at 800 MHz with the input reference frequency of 60 MHz under 1 V supply and 200 MHz with reference of 15 MHz under 0.6 V. The in-band phase noise of DPLL can be improved by nearly 20 dB by utilizing an 8-tap FIR filter and a 5-bit delay chains. Furthermore, this thesis also shows a gain-boosted two-stage ring oscillator. The PLL consumes 10.3 mW from a 1.2 V supply at 13.6 GHz output with the input reference frequency of 850 MHz. The measured phase noise is -101 dBc/Hz at 10 MHz offset.

Publications

Papers：：

[1] Xiaohua Huang,Han Liu,Woogeun Rhee,Zhihua Wang, A DS DPLL with 1b TDC, 4b DTC and 8-Tap FIR Filter For Low-Voltage Clock Generation/Modulation Systems, VLSI-DAT 2018, pp. 1 - 2, 2018.

[2] Xiaohua Huang,Han Liu,Woogeun Rhee,Zhihua Wang, A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems, VLSI-DAT 2018, pp. 1 - 4, 2018.

[3] Han Liu,Sitao Lv,Xiaohua Huang,Woogeun Rhee,Zhihua Wang, A fractional-NBB-DPLL with auto-tuned DTC and FIR filter for noise and spur reduction, RFIT 2017, pp. 238 - 240, 2017.

[4] Yajun He,Ziqiang Wang,Han Liu,Fangxu Lv,Shuai Yuan,Chun Zhang,Zhihua Wang,Hanjun Jiang, An 8.5–12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes, MWSCAS 2017, pp. 791 - 794, 2017.

[5] Yajun He,Ziqiang Wang,Han Liu,Fangxu Lv,Shuai Yuan,Chun Zhang,Xiang Xie,Hanjun Jiang, An 8.5-12.5GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes, EDSSC 2017, pp. 1 - 2, 2017.

[6] Han Liu,Woogeun Rhee,Zhihua Wang, A 10.3mW 13.6GHz Phase-Locked Loop with Boosted Gm Two-Stage Ring VCO, ICSICT 2016, 2016.

Patents：

[1] Yajun He, Ziqiang Wang, Woogeun Rhee, Han Liu, Chun Zhang, Zhihua Wang, Fule Li. A multi-protocol phase-locked loop: China, 201611104156.X[P]. 2018-10-19.