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Meng Ni

Biography

Enrollment Date: 2013

Graduation Date：2016

Degree：M.S.

Defense Date：2016.05.30

Advisors：Fule Li

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：12 Bit 1GS/s ADC Key Components Design and Optimize

Abstract:
Analog-to-Digital converter (ADC) with high sampling rate and high performance is a hot issue in analog circuit design since it plays an important role in communication base station and satellite navigation system. The research about how to raise its sampling rate while maintain the high performance never stopped. Time-interleaving ADC is a useful means to acquire high sampling rate in current. Firstly, this paper display the measure to eliminates timing mismatch in time-interleaving ADC and conclude that a shared front-end sampling circuit is necessary in this structure. Then, the paper analysis the non-linear factor in the two parts of front-end sampling circuit in sequence: input buffer and sample-and-hold amplifier. The performance of the front-end circuit impacts the ADC’s performance straightforward for its front position. This paper concludes some conventional input buffer structure and then gives a new one. According to the simulation, the new structure improves the performance with nearly no additional power consumption. This structure had been utilized in a 12bit 1GS/s time-interleaving ADC. Besides, the paper gives some other circuit design in the 12bit 1GS/s ADC and the measurement results of it, the results indicates that the ADC acquire a INL of 10LSB at 14bit level and a DNL of 0.3LSB at 14bit level. And with an input of 251MHz and a 800MS/s sampling rate, the ADC’s ENOB is 9.91bits while the SFDR is 67.54dB. While the sampling rate up to 1GS/s, the ADC acquire a ENOB of 9.25bits and a SFDR of 63.17dB. Finally, the paper gives some conclusion of the first edition circuit and optimizes it. Results shows that the ENOB increase to 12.79bits from preclude 11.9 bits, post simulation with C+CC extract shows ADC acquires 11.86bits ENOB.

Publications

Papers：：

[1] Meng Ni,Xiao Wang,Fule Li,Zhihua Wang, A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.29, No.7, pp.1416-1427, 2021.

[2] Meng Ni,Xiao Wang,Fule Li,Woogeun Rhee,Zhihua Wang, A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.PP, No.99, pp.1-14, 2021.

[3] Meng Ni,Xiao Wang,Zhe Zhou,Yang Ding,Fule Li,Woogeun Rhee,Zhihua Wang, A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC, MWSCAS 2020, pp. 345 - 348, 2020.

[4] Meng Ni,Xiao Wang,Zhe Zhou,Yang Ding,Fule Li,Woogeun Rhee,Zhihua Wang, A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique, MWSCAS 2020, pp. 341 - 344, 2020.

[5] Yining Zhang,Meng Ni,Xiaohua Huang,Woogeun Rhee,Zhihua Wang, A 3.7-mW 2.4-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation, IEEE Journal of Solid-State Circuits, Vol.54, No.2, pp. 336 - 345, 2019.

[6] Zekai Wu,Fule Li,Meng Ni,Yang Ding,Zhihua Wang, A Background Timing Skew Calibration Technique in Time-Interleaved ADCs, EDSSC 2019, pp. 1 - 3, 2019.

[7] Meng Ni,Fule Li,Jia Zhou,Zhijun Wang,Chun Zhang,Xian Tang,Zhihua Wang, A 12Bit 800MS/s time-interleaving pipeline ADC in 65nm CMOS, EDSSC 2016, pp. 391 - 394, 2016.

[8] Meng Ni,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang, A High-Speed analog front-end circuit used in a 12bit 1GSps Pipeline ADC, ASICON 2015, pp. 1 - 4, 2015.