Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.04
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research and Design on High-Performance and Low-Power Analog-to-Digital Converter
Abstract:
With the scaling down of CMOS technology, the performance of digital integrated circuits improve increasingly while analog circuit design becomes increasingly difficult. As the interface of the analog system and digital system, the performance of analog-to-digital converter (ADC) often becomes the bottleneck of the system. With the rapid development of system on chip (SoC) and digital siganal processing (DSP), ADC with high-performance and low-power has become a research focus in both academy and industry.
This thesis analyzes and summarizes the various design techniques about high-performance and low-power ADC firstly. Secondly，a 10-bit 32MS/s low-power asynchronous successive approximate register (SAR) ADC intellectual property ( IP ) is designed for Wi-Fi transceiver system in a TSMC 180nm CMOS technology. To boost the conversion speed with high power-efficiency, split-capacitor array, fully dynamic comparator and full custom dynamic SAR logic are adopted. Post-layout transient simulation with noise shows that the ADC achieves 59.3dB SNDR and 72.3dB SFDR with an input frequency of 15.14MHz at 32MS/s. At a 1.8V supply voltage, the ADC core consumes 1.38mW while the reference buffer consumes 0.12mW. The measured results show that the ADC achieves a SNR of 54.6dB and 8.8-bit ENOB with an input frequency of 1MHz.
Furthermore, in order to boost the performance of ADC with low-power, this thesis proposed a low-power ADC design which is suitable for deep sub-micron technology. It has the following characteristics: (1) Combined with pipelined ADC, SAR ADC and flash ADC, a hybrid structure ADC with only one residue amplifier is adopted. (2) Eliminating the front-end sample-and-hold amplifier (SHA) that typically precedes a pipelined ADC, it can not only eliminate its noise and distortion contribution, but also its power dissipation. (3) A multi-bit front-end is adopted in the first stage, reducing the noise, nonlinearity and power further. (4) Utilizing the range-scaling technique and 1-bit redundancy, a wider input signal swing and a smaller output swing of the inter-stage can be achieved. It can not only raise the signal to noise ratio（SNR） in the low supply voltage, but also simplify the op-amp design, thus saving power. (5) Using the correlated level-shifting technique to relax the requirements of the op-amp’s direct current (DC) gain and output swing. (6) By applying the capacitor sharing technique between the first stage and the second stage, it further saves power.
Finally, based on the proposed high-performance and low-power ADC design, a 14-bit 200MS/s ADC is implemented in a TSMC 65nm general purpose (GP) CMOS technology. The total area including pads is about 1mm2, while the ADC core only occupies 0.0875mm2. Post-layout transient simulation results with noise demonstrate that the ADC achieves 4.9dB SNDR and 84.2dB SFDR with an input frequency of 93.19MHz. The ADC consumes 31.5mW totally at a 1.2V supply voltage, while the ADC core consumes only 25.6mW and the clock receiver circuit consumes 5.63mW, respectively.