Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.29
Advisors：Baoyong Chi
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Key Techniques of 40GHz PLL Frequency Synthesizer and Its Clock Distribution Networks
Abstract:
In recent years, wireless communication technology has witnessed rapid development. The development trend substantially goes towards a higher date rate. From the first generation mobile communication to the mainstream third generation mobile communication, and even the next generation wireless communication technology ,they have reached Mbps data rate. However, due to the mass data transfer requirement for the video transmission, it is needed to search a system with higher transmission data rate. The millimeter wave technology has a high carrier frequency with a GHz available bandwidth, and is very suitable for high data rate systems. The IEEE 802.15.3c protocol provides a standard for 60GHz short-range millimeter-wave communication. In communication system, the frequency synthesizer as well as its clock distribution network is a crucial module, which directly affects the various performance of the communication system. This research is proposed to design for a frequency synthesizer as well as its clock distribution network to support the 60 GHz millimeter wave communication system.
The work of this thesis consists of two parts, one part is the 40GHz PLL frequency synthesizer design. Circuit modules include: differential tuning LC-VCO, 40G buffer, quadrature output injection locked frequency divider, 20G buffer, the CML divider, multimode divider MMD, the phase frequency PFD, charge pump CP . The differential tuning LC-VCO, quadrature output injection locked frequency divider, the charge pump CP are the most innovative modules. The frequency synthesizer is an integer PLL with center frequency of 40GHz, tuning range of 10%, and is implemented in 65nm CMOS. Except the PFD and CP is powered by 2.5V supply, the power supply voltage of the rest modules is 1V. The power consumption of the entire phase-locked loop is 38mA.
Another work of this thesis is a clock distribution network with 4-1 mux function. With higher data rate, the entire system has greater design complexity. So we use the variable data rate system design: data rate could be set to 10G,5G, 2.5G, and 1.25Gbps. Therefore, in the receiver, clock is variable, which needs to design a 4-1 MUX circuit. Ultimately, our designed clock distribution network meets the requirements: the frequency range is 10% and achieves approximately sine wave and a certain level amplitude of output in various process corners. The supply voltage is 1V, and the power consumption is 20mA at maximum, 14mA at minimum.