题目/Title：
                        A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication

作者/Author：况立雪,池保勇,陈磊,贾雯,王志华
                        Lixue Kuang,Baoyong Chi,Lei Chen,Wen Jia,Zhihua Wang

期刊/Journal：半导体学报 Journal of Semiconductors

年份/Issue Date：2014.Dec.

卷（期）及页码/Volume（No.）&pages：Vol.35, No.12, pp. 125002-1-6

摘要/Abstract：

A 40-GHz phase-locked loop (PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator (VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector (PFD) and the charge pump (CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is-97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 mW, including all the buffers.