Biography
Enrollment Date: 2009
Graduation Date:2015
Degree:Ph.D.
Defense Date:2014.12.26
Advisors:Zhihua Wang Baoyong Chi
Department:Institute of Microelectronics,Tsinghua University
Title of Dissertation/Thesis:Research on Key Techniques of CMOS Mm-wave High Data-Rate Wireless Transceivers
Abstract:
Along with the rapid progress of wireless communication techniques, the traditional spectrum that is allocated for wireless communication becomes more and more congested, while the demands of high data-rate wireless link remains growing. Compared to main stream wireless communications, there are three intrinsic advantages with the wireless communication in 60-GHz bands: low interference, small devices, and high data-rate. Furthermore, the CMOS technology scaling is a strong guarantee for the low-cost and widespread use of 60-GHz wireless transceivers in the future. In this dissertation, the key techniques of 60-GHz CMOS high data-rate wireless transceivers chip are studied.
This dissertation proposes a co-design technique of the millimeter-wave (mm-wave) on-chip transmit/receive (T/R) switch and the low noise amplifier (LNA) / power amplifier (PA). With the co-design technique, the effects of insertion loss that introduced by the T/R switch could be minimized, and the matching bandwidth of the front-end could be extended. With the T/R switch integrated on chip, the number of antennas could be reduced, thus reducing the system size and lower the total cost.
This dissertation proposes a dual-mode PA structure based on the stacked-transistor technique, and has implemented the first 60-GHz dual-mode PA in bulk CMOS that employs the stacked-transistor technique. The measured results show that in the high-power (HP) mode, the PA achieves a peak power-added efficiency (PAE) over 20%, and a 1-dB output power higher than 10 dBm. In the low-power (LP) mode, the saturated output power of the PA is higher than 10 dBm. The PAE at 10-dBm output power is improved by 2.8x (10.6% versus 3.8%) by utilizing the LP mode compared with the HP-mode-only PA.
In this dissertation, multiple bandwidth-extension techniques for mm-wave high data-rate wireless transceivers are studied, including the high-order LC network wideband impedance matching technique, distributed amplifier technique, π-network inter-stage coupling. These techniques are modified to be utilized in the design of wideband transmitter/receiver (TX/RX) link and wider than 5.0-GHz TX/RX link bandwidth has been achieved.
Based on the above techniques, two 60-GHz transceivers are implemented in 65nm CMOS. The first transceiver is fully-integrated, including on-chip T/R switch, mm-wave front-end modules, programmable-gain amplifier, fully-differential phase-locked loop frequency synthesizer, and QPSK modulator/demodulator. The transceiver achieves a 5-Gb/s QPSK transmission with comparatively low power dissipation. The second one is a four-channel transceiver based on IEEE 802.11ad. A dual-mode power amplifier and a high-linearity transmit/receive switch are integrated, and the transceiver supports four-channel switching. Besides, the power dissipation is lowered, and the chip area is also reduced compared to the first transceiver.