Biography
Enrollment Date: 2007
Graduation Date：2010
Degree：M.S.
Defense Date：2010.06.04
Advisors：Baoyong Chi
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Analog Baseband Circuits for Short-range Wireless Communicaiton
Abstract:
A low power high data rate ASK IF receiver, aimed to be used in the portable device of the wireless endoscopy system, is proposed in the first part of this thesis. It consists of one digital-control AGC loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of PGA in the AGC loop is adjusted discretely by a gain control block to eliminate the multi-digit A/D converter. From the concept of scrambler, a certain number of consecutive ‘0’ or ‘1’ will not appear in the received bit stream. Once it occurs, the amplitude of signal received by the antenna must be too small or too large. Then the gain-control block will adjust the gain of PGA in order to obtain suitable output signal amplitude of the AGC loop. Due to the high sensitivity of the ASK detector, a large controllable input range can be obtained in the AGC loop. The ASK IF receiver has been implemented in UMC 0.18μm CMOS and the overall current consumption is 1.21mA with a supply voltage of 1.8V. The ASK receiver achieves a 2Mbps data rate with an IF carrier frequency of 10MHz and an input signal amplitude range from 180uV to 900mV with the BER less than 1%. In order to support multi-mode short-range wireless communication applications, an IF analog circuit used in a multi-mode multi-band configurable wireless transceiver is presented in the second part of this thesis. It consists of two fixed-gain amplifiers (FGA), two programmable gain amplifiers (PGA), a complex band-pass filter with configurable bandwidth， and a received signal strength indicator (RSSI). In order to obtain the flat group delay characteristic, a third-order Bessel active RC structure is adopted to implement the complex band-pass filter. At the same time, to avoid the problems introduced by the errors of the values of the integrated resistors and capacitors due to the process and temperature variation, the on-chip automatic frequency tuning circuit is designed. The IF analog circuit provides 22dB~58dB variable gain, 2MHz/1MHz/0.5MHz bandwidth and RSSI function. The IF analog circuit has been implemented in UMC 0.18 CMOS, and the measured results show that the circuit has achieved the scheduled design goal, and the overall current consumption is 5mA with a supply voltage of 1.8V.