Enrollment Date : 2016
Anticipated Graduation Date：2019
Type of Candidate：Master Candidate
Advisors：Hong Chen
Department：Institute of Microelectronics，Tsinghua University
Research Area：
[1] Jiawei Wang, Hao Xu, Ziqiang Wang, Haikun Jia, Hanjun Jiang, Chun Zhang, Zhihua Wang, A 128 Gbps PAM-4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS, IET CIRCUITS DEVICES & SYSTEMS, Vol.17, No.3, pp.174-179, 2023.
[2] Yi Zhong, Mingtao Zhan, Wei Wang, Xiyuan Tang, Lu Jie, Nan Sun, An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS, CICC 2023, pp.1-2, 2023.
[3] Shiyan Sun, An’an Li, Yingtao Ding, Zipeng Chen, Wei Wang, Sijia Jiang, Zhiming Chen, Baoyong Chi, A Ka-band calibratable phased-array front-end chip with high element-consistency, Science China Information Sciences, Vol.65, pp. 229401:1–229401:2, 2022.
[4] Xiangyu Li, Gongning Luo, Wei Wang, Kuanquan Wang, Yue Gao, Shuo Li, Hematoma Expansion Context Guided Intracranial Hemorrhage Segmentation and Uncertainty Estimation, IEEE Journal of Biomedical and Health Informatics, Vol.26, No.3, pp.1140-1151, 2022.
[5] Jiahao Zhao, Xuansheng Ji, Su Han, Ziwei Wang, Woogeun Rhee, Zhihua Wang, A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction, ICTA 2022, pp.74-75, 2022.
[6] Ziqiang Wang, Dengjie Wang, Xin Wu, Jiawei Wang, Hao Xu, Chun Zhang, Hong Chen, Zhihua Wang, A 44 Gbps PAM-4 Transmitter with Resistance Feedback 4:1 MUX in 65nm CMOS, ICSICT 2022, pp.1-3, 2022.
[7] Dengjie Wang,Ziqiang Wang,Hao Xu,Jiawei Wang,Zeliang Zhao,Chun Zhang,Zhihua Wang,Hong Chen, A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.PP, No.99, pp.1-14, 2021.
[8] Peilin Yang,Xiao Wang,Chengwei Wang,Fule Li,Hanjun Jiang,Zhihua Wang, A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.28, No.9, pp. 2004 - 2013, 2020.
[9] Chengwei Wang,Xiao Wang,Yang Ding,Fule Li,Zhihua Wang, A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique, ISCAS 2018, pp. 1 - 5, 2018.
[10] Xiao Wang,Chengwei Wang,Fule Li,Zhihua Wang, A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process, ISCAS 2018, pp. 1 - 5, 2018.
[11] Zekai Wu,Chengwei Wang,Yang Ding,Fule Li,Zhihua Wang, An ADC Input Buffer with Optimized Linearity, ICSICT 2018, pp. 1 - 3, 2018.
[12] Xinpeng Xing,Peng Zhu,Hui Liu,Wei Wang,Georges Gielen, A power-efficient reconfigurable two-step VCO-based ADC for software-defined radio, ASICON 2017, pp. 620 - 623, 2017.
[13] Yawei Wang,Songping Mai,Chun Zhang, A high-efficiency, low-power wireless power and data frontend for implantable applications, EDSSC 2014, pp. 1 - 2, 2014.
[14] Yawei Wang,Songping Mai,Chun Zhang, A low-power, 16-channel implantable neurostimulator, EDSSC 2014, pp. 1 - 2, 2014.
[1] Liji Wu, Jian Wu, Xiangmin Zhang, Xiangyu Li, Dewei Wang. System and method for actively defending hardware Trojan on storage path: China, 202010294220.5[P].
[2] Fule Li, Chengwei Wang, Wen Jia, Zhihua Wang. A method for improving the output accuracy of a pipelined ADC and an analog to digital converter: China, 201710743591.5[P]. 2020-12-08.
[3] Yiyi Ren, Junhong Lv, Wei Wang, Ying Zhou, Xiang Xie, Guolin Li, Zhihua Wang. Low-complexity gesture extracting and gesture depth acquiring method: China, 201310214597.5[P]. 2016-02-24.
[4] Yiyi Ren, Ying Zhou, Junhong Lv, Wei Wang, Xiang Xie, Guolin Li, Zhihua Wang. 3D获取系统的校准方法: China, 201310201810.9[P]. 2016-05-18.
[5] Ying Zhou, Yiyi Ren, Junhong Lv, Wei Wang, Xiang Xie, Guolin Li, Zhihua Wang. Partition method for orderly extracting point cloud on ground: China, 201310185363.2[P]. 2016-04-20.