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Yi Chen

Biography

Enrollment Date: 2006

Graduation Date：2009

Degree：M.S.

Defense Date：2009.06.08

Advisors：Zhihua Wang

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Design of A/D Converters for the Auxiliary System of Orthopedic Implants

Abstract:
The artificial joint replacement has important significances for patients with osteoarthritis to improve their qualities of life. In the process of implantation, auxiliary installation system can provide scientific basis for the doctors’ operation. After the artificial joint is implanted in patients’ bodies, wireless monitoring system can help doctors find the problems during the use of implanted artificial joint. Analog-to-Digital Converter (ADC) is a key part of the wireless monitoring system and auxiliary installation system. This thesis studies structures and characteristics of different kinds of ADCs and designs appropriate ADCs which satisfy the requirements of wireless monitoring system and auxiliary installation system. This thesis presents a low power cyclic ADC design for the wireless monitoring system of the orthopedic implants. Besides the differential two-step cyclic A/D conversion core, the ADC also includes an analog multiplexer and a single-to-differential conversion circuit for the specific application. The prototype chip has been fabricated in UMC 0.18μm CMOS Mixed-mode process. The core of ADC without PAD occupies only 0.12mm2. With a 304.7Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of ADC is only 12.5μW in normal working mode and less than 150nW in sleep mode. The test result shows the performance of proposed ADC satisfies the requirement of the wireless monitor system. This thesis also presents a high precision successive approximation ADC (SAR ADC) design for the auxiliary installation system of orthopedic implants. The proposed SAR ADC consists of an ADC conversion core and a calibration module. The calibration module is implemented on MCU of the system and validated on FPGA. The calibration algorithm is based on the perceptron learning rule. The time for calibration is about 10ms. Behavior simulation of calibration algorithm shows after calibration the ENOB of ADC can reach 15.3 bit with 0.1% capacitance mismatch. ADC core includes a non-binary segmented capacitive DAC with radix of 1.8 and a high speed and high resolution comparator which is composed of six preamplifiers and a latch. The core of SAR ADC has been fabricated in UMC 0.18μm 1P6M CMOS process. The chip size is 2mm×2mm. The post-simulation of core circuit of the proposed ADC shows with 1-MHz sampling frequency, the proposed ADC can reach above 117dBc of SFDR and 23.8mW of power consumption. The simulation results show that the ADC core can work well and the performance of the ADC satisfies the requirement of the system. The thesis also presents the test scheme for high precision SAR ADC.

Publications

Papers：：

[1] Yanting Ren,Liji Wu,Hexin Li,Xiangyu Li,Xiangmin Zhang,An Wang,Hongyi Chen, Key recovery against 3DES in CPU smart card based on improved correlation power analysis, Tsinghua Science and Technology, Vol.21, No.2, pp. 210 - 220, 2016.

[2] Yi Chen,Fule Li,Hong Chen,Chun Zhang,Zhihua Wang, A low power cyclic ADC design for a wireless monitoring system for orthopedic implants, Chinese Journal of Semiconductors, Vol.30, No.8, pp. 147 - 152, 2010.

[3] Yi Chen,Fule Li,Hong Chen,Chun Zhang,Zhihua Wang, A Low Power Cyclic ADC Design for the Wireless Monitoring System of the Orthopedic Implants, Chinese Journal of Semiconductors, Vol.30, No.8, pp. 147 - 152, 2009.

[4] Baoyong Chi,Li Zhang,Woogeun Rhee,Zhihua Wang,Hongyi Chen, A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesizer, International Journal of Electronics, Vol.96, No.10, pp. 1039 - 1056, 2009.

[5] Hong Chen,Ming Liu,Wenhan Hao,Yi Chen,Chun Zhang,Zhihua Wang, Low-Power Circuits for the Bidirectional Wireless Monitoring System of the Orthopedic Implants, IEEE Transactions on Biomedical Circuits and Systems, Vol.3, No.6, pp. 437 - 443, 2009.

[6] Li Zhang,Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Wang, D.,Zhihua Wang,Hongyi Chen, A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops, IEEE Journal of Solid-State Circuits, Vol.44, No.11, pp. 2922 - 2934, 2009.

[7] Haolu Xie,Xin Wang,A. Wang,Bin Zhao,Yumei Zhou,Bo Qin,Hongyi Chen,Zhihua Wang, A varying pulse width 5th-derivative gaussian pulse generator for UWB transceivers in CMOS, RWS 2008, pp. 171 - 174, 2008.

[8] Hong Chen,Chen Jia,Yi Chen,Ming Liu,Chun Zhang,Zhihua Wang, A low-power IC design for the wireless monitoring system of the orthopedic implants, CICC 2008, pp. 363 - 366 , 2008.

[9] Li Zhang,Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang,Hongyi Chen,Wang, D., A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops, A-SSCC 2008, pp. 417 - 420, 2008.

[10] Yanqing Ning,Zhihua Wang,Hongyi Chen, Structure and Feature of Cross-Coupled MOS FET in CMOS LC VCO, Semiconductor Technology, Vol.32, No.7, pp. 21 - 25, 2007.

[11] Bo Qin,Ming Liu,Huiming Zhong,Liang Chen,Lifang Liu,Wenyu Xiao,Chen Jia,Zhiliang Chen,Hongyi Chen, Design of Control/Driver Chip for 65k Color PM-OLED, Journal of Tsinghua University (Science and Technology), Vol.47, No.7, pp. 36 - 40, 2007.

[12] Yanqing Ning,Zhihua Wang,Hongyi Chen, Pseudo Operation Point and Design of Ultra Broadband CMOS LC VCO, Journal of Electron Devices, Vol.30, No.2, pp. 349 - 352, 2007.

[13] Yanqing Ning,Baoyong Chi,Zhihua Wang,Hongyi Chen, A CMOS LC VCO with 3. 2-6. 1GHz Tuning Range, Chinese Journal of Semiconductors, Vol.28, No.4 pp. 526 - 529, 2007.

[14] Li Zhang,Zhihua Wang,Hongyi Chen, A 5GHz CMOS VCO for IEEE 802.11a WLAN application, Chinese Journal of Electronics, Vol.16, No.1, pp. 66 - 68, 2007.

[15] Xuguang Sun,Chun Zhang,Yongming Li,Zhihua Wang,Hongyi Chen, Design of Several Key Circuits of UHF Passive RFID Tag, China Integrated Circuit, Vol.16, No.1, pp. 29 - 35, 2007.

[16] Li Zhang,Baoyong Chi,Zhihua Wang,Hongyi Chen,Jinke Yao,Ende Wu, A 2-GHz 6.1-mA fully-differential CMOS phase-locked loop, ISCAS 2007, pp. 2447 - 2450, 2007.

[17] Li Zhang,Ende Wu,Zhihua Wang,Hongyi Chen, CMOS voltage-controlled oscillator with automatic amplitude control, Journal of Tsinghua University (Science and Technology), Vol.46, No.7, pp. 1337 - 1340, 2006.

[18] Bo Qin,Chen Jia,Zhiliang Chen,Hongyi Chen, A 1V MNC Bandgap Reference with High Temperature Stability, Chinese Journal of Semiconductors, Vol.27, No.11, pp. 2035 - 2039, 2006.

[19] Ruifeng Liu,Yongming Li,Hongyi Chen,Zhihua Wang, EVM estimation by analyzing transmitter imperfections mathematically and graphically, Analog Integrated Circuits and Signal Processing, Vol.48, No.3, pp. 257 - 262, 2006.

[20] Haolu Xie,Siqiang Fan,A. Wang,Albert Wang,Zhihua Wang,Hongyi Chen, A Pulse-Based Full-Band UWB Transceiver SoC in 0.18μm SiGe BiCMOS, SOCC 2006, pp. 73 - 76, 2006.

[21] Li Zhang,Baoyong Chi,Zhihua Wang,Hongyi Chen,Ende Wu, A Low Power 440-MHz Pulse-Swallow-Divider Combination Synchronization-Asynchronism-Hybrid Frequency Divider, MWSCAS 2006, pp. 566 - 568, 2006.

[22] Li Zhang,Baoyong Chi,JinKeYao,Zhihua Wang,Hongyi Chen, A 2-GHz Low Power Differentially Tuned CMOS Monolithic LC-VCO, ISCE 2006, pp. 1 - 4, 2006.

[23] Bo Qin,Chen Jia,Zhiliang Chen,Hongyi Chen, A 1V MNC Bandgap Reference with High Temperature Stability, ICCCAS 2006, pp. 2205 - 2209, 2006.

[24] Leibo Liu,Ning Chen,Chun Zhang,Hongying Meng,Li Zhang,Zhihua Wang,Hongyi Chen, An ASIC implementation of JPEG2000 encoder, Chinese Journal of Electronics, Vol.14, No.4, pp. 603 - 608, 2005.

[25] Li Zhang,Jinke Yao,Ende Wu,Baoyong Chi,Zhihua Wang,Hongyi Chen, A CMOS Fully Differential Σ-Δ A Frequency Synthesizer for 2-Mb/s GMSK Modulation, ICM 2005, pp. 6 - 9, 2005.

[26] Yanqing Ning,Zhihua Wang,Hongyi Chen, Design of ultra wideband MOS differential VCO, ASICON 2005, pp. 441 - 445, 2005.

[27] Liu, Leibo,Ning Chen,Hongying Meng,Li Zhang,Zhihua Wang,Hongyi Chen, A VLSI architecture of JPEG2000 encoder, IEEE Journal of Solid-State Circuits, Vol.39, No.11, pp. 2032 - 2040, 2004.

[28] Li Zhang,Zhihua Wang,Hongyi Chen, A 5-GHz CMOS VCO for IEEE 802.11a WLAN application, ICSICT 2004, pp. 1311 - 1314, 2004.

[29] Leibo Liu,Dejian Li,Xujin Wang,Hongying Meng,Zhihua Wang,Hongyi Chen,Yuwen Xia, DWT and EBCOT VLSI architecture for JPEG2000, Journal of Tsinghua University (Science and Technology), Vol.43, No.4, pp. 573 - 576, 2003.

[30] Leibo Liu,Ning Chen,Hongying Meng,Li Zhang,Zhihua Wang,Hongyi Chen, A VLSI chip of SCLA based 2-D DWT/IDWT, ASICON 2003, pp. 898 - 901, 2003.

[31] Leibo Liu,Dejian Li,Li Zhang,Zhihua Wang,Hongyi Chen, A VLSI architecture of EBCOT encoder for JPEG2000, ASICON 2003, pp. 882 - 885, 2003.

[32] Leibo Liu,Xuejin Wang,Hongying Meng,Li Zhang,Zhihua Wang,Hongyi Chen, A VLSI architecture of spatial combinative lifting algorithm based 2-D DWT/IDWT, APCCAS 2002, pp. 299 - 304, 2002.